Michael West
dc86b52fd7
Sets time increment based on tick rate and sample rate instead of assuming one tick per sample. Defaults to legacy behavior. Minor compat number bumped on DUC and DDC blocks. Signed-off-by: Michael West <michael.west@ettus.com> Original-commit: 12dfb97c8efce40494efb35bdd81d06b6f8b9b62
389 lines
16 KiB
Verilog
389 lines
16 KiB
Verilog
//
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// Copyright 2019 Ettus Research, a National Instruments Company
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfnoc_block_ddc
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//
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// Description: An digital down-converter block for RFNoC.
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//
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// Parameters:
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//
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// THIS_PORTID : Control crossbar port to which this block is connected
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// CHDR_W : AXIS CHDR interface data width
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// NUM_PORTS : Number of DDCs to instantiate
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// MTU : Maximum transmission unit (i.e., maximum packet size) in
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// CHDR words is 2**MTU.
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// NUM_HB : Number of half-band decimation blocks to include (0-3)
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// CIC_MAX_DECIM : Maximum decimation to support in the CIC filter
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//
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module rfnoc_block_ddc #(
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parameter THIS_PORTID = 0,
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parameter CHDR_W = 64,
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parameter NUM_PORTS = 2,
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parameter MTU = 10,
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parameter NUM_HB = 3,
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parameter CIC_MAX_DECIM = 255
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) (
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//---------------------------------------------------------------------------
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// AXIS CHDR Port
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//---------------------------------------------------------------------------
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input wire rfnoc_chdr_clk,
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input wire ce_clk,
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// CHDR inputs from framework
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input wire [NUM_PORTS*CHDR_W-1:0] s_rfnoc_chdr_tdata,
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input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tlast,
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input wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tvalid,
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output wire [ NUM_PORTS-1:0] s_rfnoc_chdr_tready,
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// CHDR outputs to framework
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output wire [NUM_PORTS*CHDR_W-1:0] m_rfnoc_chdr_tdata,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tlast,
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output wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tvalid,
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input wire [ NUM_PORTS-1:0] m_rfnoc_chdr_tready,
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// Backend interface
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input wire [511:0] rfnoc_core_config,
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output wire [511:0] rfnoc_core_status,
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//---------------------------------------------------------------------------
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// AXIS CTRL Port
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//---------------------------------------------------------------------------
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input wire rfnoc_ctrl_clk,
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// CTRL port requests from framework
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input wire [31:0] s_rfnoc_ctrl_tdata,
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input wire s_rfnoc_ctrl_tlast,
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input wire s_rfnoc_ctrl_tvalid,
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output wire s_rfnoc_ctrl_tready,
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// CTRL port requests to framework
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output wire [31:0] m_rfnoc_ctrl_tdata,
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output wire m_rfnoc_ctrl_tlast,
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output wire m_rfnoc_ctrl_tvalid,
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input wire m_rfnoc_ctrl_tready
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);
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// These are the only supported values for now
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localparam ITEM_W = 32;
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localparam NIPC = 1;
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localparam COMPAT_MAJOR = 16'h0;
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localparam COMPAT_MINOR = 16'h1;
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`include "rfnoc_block_ddc_regs.vh"
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`include "../../core/rfnoc_axis_ctrl_utils.vh"
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//---------------------------------------------------------------------------
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// Signal Declarations
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//---------------------------------------------------------------------------
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wire ctrlport_req_wr;
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wire ctrlport_req_rd;
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wire [19:0] ctrlport_req_addr;
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wire [31:0] ctrlport_req_data;
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wire ctrlport_req_has_time;
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wire [63:0] ctrlport_req_time;
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wire ctrlport_resp_ack;
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wire [31:0] ctrlport_resp_data;
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wire [NUM_PORTS*ITEM_W-1:0] m_axis_data_tdata;
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wire [ NUM_PORTS-1:0] m_axis_data_tlast;
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wire [ NUM_PORTS-1:0] m_axis_data_tvalid;
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wire [ NUM_PORTS-1:0] m_axis_data_tready;
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wire [ NUM_PORTS*64-1:0] m_axis_data_ttimestamp;
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wire [ NUM_PORTS-1:0] m_axis_data_thas_time;
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wire [ 16*NUM_PORTS-1:0] m_axis_data_tlength;
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wire [ NUM_PORTS-1:0] m_axis_data_teob;
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wire [ NUM_PORTS*128-1:0] m_axis_data_tuser;
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wire [NUM_PORTS*ITEM_W-1:0] s_axis_data_tdata;
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wire [ NUM_PORTS-1:0] s_axis_data_tlast;
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wire [ NUM_PORTS-1:0] s_axis_data_tvalid;
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wire [ NUM_PORTS-1:0] s_axis_data_tready;
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wire [ NUM_PORTS*128-1:0] s_axis_data_tuser;
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wire [ NUM_PORTS-1:0] s_axis_data_teob;
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wire [ NUM_PORTS*64-1:0] s_axis_data_ttimestamp;
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wire [ NUM_PORTS-1:0] s_axis_data_thas_time;
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//---------------------------------------------------------------------------
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// NoC Shell
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//---------------------------------------------------------------------------
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wire ce_rst;
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noc_shell_ddc #(
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.THIS_PORTID (THIS_PORTID),
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.CHDR_W (CHDR_W),
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.MTU (MTU),
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.NUM_PORTS (NUM_PORTS)
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) noc_shell_ddc_i (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.ce_clk (ce_clk),
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.rfnoc_chdr_rst (),
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.rfnoc_ctrl_rst (),
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.ce_rst (ce_rst),
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.rfnoc_core_config (rfnoc_core_config),
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.rfnoc_core_status (rfnoc_core_status),
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.s_rfnoc_chdr_tdata (s_rfnoc_chdr_tdata),
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.s_rfnoc_chdr_tlast (s_rfnoc_chdr_tlast),
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.s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
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.s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
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.m_rfnoc_chdr_tdata (m_rfnoc_chdr_tdata),
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.m_rfnoc_chdr_tlast (m_rfnoc_chdr_tlast),
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.m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
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.m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
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.s_rfnoc_ctrl_tdata (s_rfnoc_ctrl_tdata),
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.s_rfnoc_ctrl_tlast (s_rfnoc_ctrl_tlast),
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.s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
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.s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
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.m_rfnoc_ctrl_tdata (m_rfnoc_ctrl_tdata),
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.m_rfnoc_ctrl_tlast (m_rfnoc_ctrl_tlast),
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.m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
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.m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
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.ctrlport_clk (),
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.ctrlport_rst (),
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.m_ctrlport_req_wr (ctrlport_req_wr),
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.m_ctrlport_req_rd (ctrlport_req_rd),
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.m_ctrlport_req_addr (ctrlport_req_addr),
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.m_ctrlport_req_data (ctrlport_req_data),
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.m_ctrlport_req_has_time (ctrlport_req_has_time),
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.m_ctrlport_req_time (ctrlport_req_time),
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.m_ctrlport_resp_ack (ctrlport_resp_ack),
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.m_ctrlport_resp_data (ctrlport_resp_data),
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.axis_data_clk (),
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.axis_data_rst (),
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.m_in_axis_tdata (m_axis_data_tdata),
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.m_in_axis_tkeep (),
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.m_in_axis_tlast (m_axis_data_tlast),
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.m_in_axis_tvalid (m_axis_data_tvalid),
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.m_in_axis_tready (m_axis_data_tready),
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.m_in_axis_ttimestamp (m_axis_data_ttimestamp),
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.m_in_axis_thas_time (m_axis_data_thas_time),
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.m_in_axis_tlength (m_axis_data_tlength),
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.m_in_axis_teov (),
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.m_in_axis_teob (m_axis_data_teob),
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.s_out_axis_tdata (s_axis_data_tdata),
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.s_out_axis_tkeep ({NUM_PORTS*NIPC{1'b1}}),
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.s_out_axis_tlast (s_axis_data_tlast),
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.s_out_axis_tvalid (s_axis_data_tvalid),
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.s_out_axis_tready (s_axis_data_tready),
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.s_out_axis_ttimestamp (s_axis_data_ttimestamp),
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.s_out_axis_thas_time (s_axis_data_thas_time),
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.s_out_axis_teov ({NUM_PORTS{1'b0}}),
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.s_out_axis_teob (s_axis_data_teob)
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);
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//---------------------------------------------------------------------------
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// Register Translation
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//---------------------------------------------------------------------------
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//
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// Each DDC block is allocated an address spaces. This block translates CTRL
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// port transactions in that space to settings bus.
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//
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//---------------------------------------------------------------------------
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wire [ 8*NUM_PORTS-1:0] set_addr;
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wire [32*NUM_PORTS-1:0] set_data;
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wire [ NUM_PORTS-1:0] set_has_time;
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wire [ NUM_PORTS-1:0] set_stb;
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wire [64*NUM_PORTS-1:0] set_time;
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wire [ 8*NUM_PORTS-1:0] rb_addr;
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reg [64*NUM_PORTS-1:0] rb_data;
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wire [ NUM_PORTS-1:0] rb_stb;
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ctrlport_to_settings_bus # (
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.NUM_PORTS (NUM_PORTS)
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) ctrlport_to_settings_bus_i (
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.ctrlport_clk (ce_clk),
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.ctrlport_rst (ce_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr),
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.s_ctrlport_req_rd (ctrlport_req_rd),
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.s_ctrlport_req_addr (ctrlport_req_addr),
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.s_ctrlport_req_data (ctrlport_req_data),
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.s_ctrlport_req_has_time (ctrlport_req_has_time),
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.s_ctrlport_req_time (ctrlport_req_time),
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.s_ctrlport_resp_ack (ctrlport_resp_ack),
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.s_ctrlport_resp_data (ctrlport_resp_data),
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.set_data (set_data),
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.set_addr (set_addr),
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.set_stb (set_stb),
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.set_time (set_time),
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.set_has_time (set_has_time),
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.rb_stb (rb_stb),
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.rb_addr (rb_addr),
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.rb_data (rb_data),
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.timestamp (64'b0)
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);
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//---------------------------------------------------------------------------
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// DDC Implementation
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//---------------------------------------------------------------------------
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// Unused signals
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wire [ NUM_PORTS-1:0] clear_tx_seqnum = 0;
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wire [16*NUM_PORTS-1:0] src_sid = 0;
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wire [16*NUM_PORTS-1:0] next_dst_sid = 0;
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localparam MAX_N = CIC_MAX_DECIM * 2 << (NUM_HB-1);
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genvar i;
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generate
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for (i = 0; i < NUM_PORTS; i = i + 1) begin : gen_ddc_chains
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wire set_stb_int = set_stb[i];
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wire [7:0] set_addr_int = set_addr[8*i+7:8*i];
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wire [31:0] set_data_int = set_data[32*i+31:32*i];
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wire [63:0] set_time_int = set_time[64*i+63:64*i];
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wire set_has_time_int = set_has_time[i];
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// Build the expected tuser CHDR header
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cvita_hdr_encoder cvita_hdr_encoder_i (
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.pkt_type (2'b0),
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.eob (m_axis_data_teob[i]),
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.has_time (m_axis_data_thas_time[i]),
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.seqnum (12'b0),
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.payload_length (m_axis_data_tlength[16*i +: 16]),
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.src_sid (16'b0),
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.dst_sid (16'b0),
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.vita_time (m_axis_data_ttimestamp[64*i +: 64]),
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.header (m_axis_data_tuser[128*i+:128])
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);
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// Extract bit fields from outgoing tuser CHDR header
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assign s_axis_data_teob[i] = s_axis_data_tuser[128*i+124 +: 1];
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assign s_axis_data_thas_time[i] = s_axis_data_tuser[128*i+125 +: 1];
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assign s_axis_data_ttimestamp[64*i+:64] = s_axis_data_tuser[128*i+ 0 +: 64];
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// TODO: Read-back register for number of FIR filter taps
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always @(*) begin
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case(rb_addr[8*i+7:8*i])
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RB_COMPAT_NUM : rb_data[64*i+63:64*i] <= {COMPAT_MAJOR, COMPAT_MINOR};
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RB_NUM_HB : rb_data[64*i+63:64*i] <= NUM_HB;
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RB_CIC_MAX_DECIM : rb_data[64*i+63:64*i] <= CIC_MAX_DECIM;
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default : rb_data[64*i+63:64*i] <= 64'h0BADC0DE0BADC0DE;
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endcase
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end
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////////////////////////////////////////////////////////////
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//
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// Timed Commands
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//
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////////////////////////////////////////////////////////////
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wire [31:0] m_axis_tagged_tdata;
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wire m_axis_tagged_tlast;
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wire m_axis_tagged_tvalid;
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wire m_axis_tagged_tready;
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wire [127:0] m_axis_tagged_tuser;
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wire m_axis_tagged_tag;
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wire out_set_stb;
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wire [7:0] out_set_addr;
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wire [31:0] out_set_data;
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wire timed_set_stb;
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wire [7:0] timed_set_addr;
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wire [31:0] timed_set_data;
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wire timed_cmd_fifo_full;
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axi_tag_time #(
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.NUM_TAGS(1),
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.SR_TAG_ADDRS(SR_FREQ_ADDR))
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axi_tag_time (
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.clk(ce_clk),
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.reset(ce_rst),
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.clear(clear_tx_seqnum[i]),
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.tick_rate(16'd1),
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.timed_cmd_fifo_full(timed_cmd_fifo_full),
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.s_axis_data_tdata(m_axis_data_tdata[i*ITEM_W+:ITEM_W]), .s_axis_data_tlast(m_axis_data_tlast[i]),
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.s_axis_data_tvalid(m_axis_data_tvalid[i]), .s_axis_data_tready(m_axis_data_tready[i]),
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.s_axis_data_tuser(m_axis_data_tuser[128*i+:128]),
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.m_axis_data_tdata(m_axis_tagged_tdata), .m_axis_data_tlast(m_axis_tagged_tlast),
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.m_axis_data_tvalid(m_axis_tagged_tvalid), .m_axis_data_tready(m_axis_tagged_tready),
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.m_axis_data_tuser(m_axis_tagged_tuser), .m_axis_data_tag(m_axis_tagged_tag),
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.in_set_stb(set_stb_int), .in_set_addr(set_addr_int), .in_set_data(set_data_int),
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.in_set_time(set_time_int), .in_set_has_time(set_has_time_int),
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.out_set_stb(out_set_stb), .out_set_addr(out_set_addr), .out_set_data(out_set_data),
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.timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data));
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// Hold off reading additional commands if internal FIFO is full
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assign rb_stb[i] = ~timed_cmd_fifo_full;
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////////////////////////////////////////////////////////////
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//
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// Reduce Rate
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//
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////////////////////////////////////////////////////////////
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wire [31:0] sample_in_tdata, sample_out_tdata;
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wire sample_in_tuser, sample_in_eob;
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wire sample_in_tvalid, sample_in_tready, sample_in_tlast;
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wire sample_out_tvalid, sample_out_tready;
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wire clear_user;
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wire nc;
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axi_rate_change #(
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.WIDTH(33),
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.MAX_N(MAX_N),
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.MAX_M(1),
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.SR_N_ADDR(SR_N_ADDR),
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.SR_M_ADDR(SR_M_ADDR),
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.SR_CONFIG_ADDR(SR_CONFIG_ADDR),
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.SR_TIME_INCR_ADDR(SR_TIME_INCR_ADDR))
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axi_rate_change (
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.clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
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.src_sid(src_sid[16*i+15:16*i]), .dst_sid(next_dst_sid[16*i+15:16*i]),
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.set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
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.i_tdata({m_axis_tagged_tag,m_axis_tagged_tdata}), .i_tlast(m_axis_tagged_tlast),
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.i_tvalid(m_axis_tagged_tvalid), .i_tready(m_axis_tagged_tready),
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.i_tuser(m_axis_tagged_tuser),
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.o_tdata({nc,s_axis_data_tdata[i*ITEM_W+:ITEM_W]}), .o_tlast(s_axis_data_tlast[i]), .o_tvalid(s_axis_data_tvalid[i]),
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.o_tready(s_axis_data_tready[i]), .o_tuser(s_axis_data_tuser[128*i+:128]),
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.m_axis_data_tdata({sample_in_tuser,sample_in_tdata}), .m_axis_data_tlast(sample_in_tlast),
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.m_axis_data_tvalid(sample_in_tvalid), .m_axis_data_tready(sample_in_tready),
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.s_axis_data_tdata({1'b0,sample_out_tdata}), .s_axis_data_tlast(1'b0),
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.s_axis_data_tvalid(sample_out_tvalid), .s_axis_data_tready(sample_out_tready),
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.warning_long_throttle(),
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.error_extra_outputs(),
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.error_drop_pkt_lockup());
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assign sample_in_eob = m_axis_tagged_tuser[124]; //this should align with last packet output from axi_rate_change
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////////////////////////////////////////////////////////////
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//
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// Digital Down Converter
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//
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////////////////////////////////////////////////////////////
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ddc #(
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.SR_FREQ_ADDR(SR_FREQ_ADDR),
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.SR_SCALE_IQ_ADDR(SR_SCALE_IQ_ADDR),
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.SR_DECIM_ADDR(SR_DECIM_ADDR),
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.SR_MUX_ADDR(SR_MUX_ADDR),
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.SR_COEFFS_ADDR(SR_COEFFS_ADDR),
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.NUM_HB(NUM_HB),
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.CIC_MAX_DECIM(CIC_MAX_DECIM))
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ddc (
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.clk(ce_clk), .reset(ce_rst),
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.clear(clear_user | clear_tx_seqnum[i]), // Use AXI Rate Change's clear user to reset block to initial state after EOB
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.set_stb(out_set_stb), .set_addr(out_set_addr), .set_data(out_set_data),
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.timed_set_stb(timed_set_stb), .timed_set_addr(timed_set_addr), .timed_set_data(timed_set_data),
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.sample_in_tdata(sample_in_tdata), .sample_in_tlast(sample_in_tlast),
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.sample_in_tvalid(sample_in_tvalid), .sample_in_tready(sample_in_tready),
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.sample_in_tuser(sample_in_tuser), .sample_in_eob(sample_in_eob),
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.sample_out_tdata(sample_out_tdata), .sample_out_tlast(),
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.sample_out_tvalid(sample_out_tvalid), .sample_out_tready(sample_out_tready)
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);
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|
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end
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endgenerate
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endmodule
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