51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
//
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// Copyright 2015 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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module pps_generator #(
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parameter CLK_FREQ = 32'd10_000_000, //Min:10kHz, Max:4GHz
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parameter DUTY_CYCLE = 25,
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parameter PIPELINE = "NONE" // Optional register on output? {"NONE", "OUT"}
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) (
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input clk,
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input reset,
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output pps
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);
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reg [31:0] count = 32'h0;
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always @(posedge clk) begin
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if (reset) begin
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count <= 32'd0;
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end else if (count >= CLK_FREQ - 1) begin
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count <= 32'd0;
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end else begin
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count <= count + 32'd1;
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end
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end
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wire pps_int;
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assign pps_int = (count < ((CLK_FREQ / 100) * DUTY_CYCLE));
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generate
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if (PIPELINE == "OUT") begin : gen_pipeline_out
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// create output register and assign to output
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reg pps_reg = 1'b0;
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assign pps = pps_reg;
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always @(posedge clk) begin
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if (reset) begin
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pps_reg <= 1'b0;
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end else begin
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pps_reg <= pps_int;
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end
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end
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end else begin : gen_pipeline_none
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// no output register
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assign pps = pps_int;
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end
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endgenerate
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endmodule //pps_generator
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