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mattprost 52172aaaf3 fpga: Add Replay Block to RFNoC Core Image 
Add the Replay RFNoC block to the RFNoC core image for x300, x310, n300,
n310, n320/n321, and e320. The Replay block is contained within its own
static connection, so previous default behavior is still supported.

Signed-off-by: mattprost <matt.prost@ni.com>


Original-commit: 437381bd2cfe137c5e7e2a70aab8226bfb1c70cd
2020-09-03 15:26:33 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ip
x300: Expand DRAM address space to 1G
2020-05-18 17:50:38 -05:00
sim
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_x300.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
bus_int.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
capture_ddrlvds.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gen_ddrlvds.v
Merge FPGA repository back into UHD repository
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Makefile
Merge FPGA repository back into UHD repository
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Makefile.x300.inc
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
nirio_chdr64_adapter.v
fpga: remove liberio
2020-07-20 16:01:03 -05:00
setupenv.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
soft_ctrl.v
Merge FPGA repository back into UHD repository
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timing.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x3x0_base.lvbitx
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge_port0.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge_port1.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_core.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
x300_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_eth_interface.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_pcie_int.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_rfnoc_image_core.v
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x300_rfnoc_image_core.yml
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x300_sfpp_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x300_zpu_config.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x310_rfnoc_image_core.v
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x310_rfnoc_image_core.yml
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00