Wade Fife
98463e99d0
For HLS builds, the output file names aren't known in advance. This makes it difficult to write the Makefile to pull in the files and pass them to the build tools. This change allows you to add a directory as your HDL source so that all files in the directory will be pulled in by the build process. Original-commit: 90933d9b2faf392fd26f3f7ca32f73719614a40a
303 lines
12 KiB
Tcl
303 lines
12 KiB
Tcl
#
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# Copyright 2014-2015 Ettus Research
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#
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# ---------------------------------------------------
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# Create namespace and initialize global parameters
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# ---------------------------------------------------
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namespace eval ::vivado_utils {
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# Export commands
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namespace export \
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initialize_project \
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synthesize_design \
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check_design \
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generate_post_synth_reports \
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generate_post_place_reports \
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generate_post_route_reports \
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write_implementation_outputs \
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get_top_module \
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get_part_name \
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get_vivado_mode
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# Required environment variables
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variable g_tools_dir $::env(VIV_TOOLS_DIR)
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variable g_top_module $::env(VIV_TOP_MODULE)
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variable g_part_name $::env(VIV_PART_NAME)
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variable g_output_dir $::env(VIV_OUTPUT_DIR)
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variable g_source_files $::env(VIV_DESIGN_SRCS)
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variable g_vivado_mode $::env(VIV_MODE)
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# Optional environment variables
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variable g_verilog_defs ""
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if { [info exists ::env(VIV_VERILOG_DEFS) ] } {
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set g_verilog_defs $::env(VIV_VERILOG_DEFS)
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}
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variable g_include_dirs ""
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if { [info exists ::env(VIV_INCLUDE_DIRS) ] } {
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set g_include_dirs $::env(VIV_INCLUDE_DIRS)
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}
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}
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# ---------------------------------------------------
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# Create a new project in memory and add source files
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# ---------------------------------------------------
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proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
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variable g_top_module
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variable g_part_name
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variable g_output_dir
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variable g_source_files
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variable bd_files ""
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file delete -force $g_output_dir/build.rpt
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if {$save_to_disk == 1} {
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puts "BUILDER: Creating Vivado project ${g_top_module}_project.xpr for part $g_part_name"
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create_project -part $g_part_name ${g_top_module}_project
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} else {
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puts "BUILDER: Creating Vivado project in memory for part $g_part_name"
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create_project -in_memory -part $g_part_name
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}
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# Expand directories to include their contents (needed for HLS outputs)
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foreach src_file $g_source_files {
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if [expr [file isdirectory $src_file] == 1] {
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puts "BUILDER: Expanding Directory : $src_file"
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set dir_contents [glob $src_file/*.*]
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append design_srcs " " $dir_contents
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}
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}
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foreach src_file $g_source_files {
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set src_ext [file extension $src_file ]
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if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
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puts "BUILDER: Adding VHDL : $src_file"
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read_vhdl -library work $src_file
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} elseif [expr [lsearch {.v .vh .sv .svh} $src_ext] >= 0] {
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puts "BUILDER: Adding Verilog : $src_file"
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read_verilog $src_file
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} elseif [expr [lsearch {.xdc} $src_ext] >= 0] {
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puts "BUILDER: Adding XDC : $src_file"
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read_xdc $src_file
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} elseif [expr [lsearch {.sdc} $src_ext] >= 0] {
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puts "BUILDER: Adding SDC : $src_file"
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read_xdc $src_file
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} elseif [expr [lsearch {.xci} $src_ext] >= 0] {
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puts "BUILDER: Adding IP : $src_file"
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read_ip $src_file
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set_property generate_synth_checkpoint true [get_files $src_file]
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} elseif [expr [lsearch {.ngc .edif .edf} $src_ext] >= 0] {
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puts "BUILDER: Adding Netlist : $src_file"
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read_edif $src_file
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} elseif [expr [lsearch {.bd} $src_ext] >= 0] {
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puts "BUILDER: Adding Block Design to list (added after IP regeneration): $src_file"
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append bd_files "$src_file "
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} elseif [expr [lsearch {.bxml} $src_ext] >= 0] {
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puts "BUILDER: Adding Block Design XML to list (added after IP regeneration): $src_file"
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append bd_files "$src_file "
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} elseif [expr [lsearch {.dat} $src_ext] >= 0] {
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puts "BUILDER: Adding Data File : $src_file"
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add_files $src_file
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} else {
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puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
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}
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}
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# The 'synth_ip [get_ips *]' step causes builds in Windows to recompile various
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# pieces of the IP. This is time-consuming and unnecessary behavior, thus is removed.
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# These steps are redundant anyway since the IP builder performs both of them.
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# puts "BUILDER: Refreshing IP"
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# generate_target all [get_ips *]
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# synth_ip [get_ips *]
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#might seem silly, but we need to add the bd files after the ip regeneration.
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foreach file $bd_files {
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puts "BUILDER: Adding file from Block Design list: $file"
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add_files -norecurse $file
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}
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puts "BUILDER: Setting $g_top_module as the top module"
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set_property top $g_top_module [current_fileset]
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}
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# ---------------------------------------------------
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# Synthesize design (Shortcut for Vivado's synth_design)
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# ---------------------------------------------------
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proc ::vivado_utils::synthesize_design {args} {
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variable g_top_module
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variable g_part_name
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variable g_verilog_defs
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variable g_include_dirs
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set vdef_args ""
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foreach vdef $g_verilog_defs {
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set vdef_args [concat $vdef_args "-verilog_define $vdef"]
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}
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set incdir_args ""
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if { [string compare $g_include_dirs ""] != 0 } {
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set incdir_args "-include_dirs $g_include_dirs"
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}
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set synth_cmd "synth_design -top $g_top_module -part $g_part_name"
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set synth_cmd [concat $synth_cmd $vdef_args]
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set synth_cmd [concat $synth_cmd $incdir_args]
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set synth_cmd [concat $synth_cmd $args]
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puts "BUILDER: Synthesizing design"
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eval $synth_cmd
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}
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# ---------------------------------------------------
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# Check design (Shortcut for Vivado's synth_design -rtl)
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# ---------------------------------------------------
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proc ::vivado_utils::check_design {args} {
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variable g_top_module
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variable g_part_name
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variable g_verilog_defs
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variable g_include_dirs
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set vdef_args ""
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foreach vdef $g_verilog_defs {
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set vdef_args [concat $vdef_args "-verilog_define $vdef"]
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}
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set incdir_args ""
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if { [string compare $g_include_dirs ""] != 0 } {
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set incdir_args "-include_dirs $g_include_dirs"
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}
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set synth_cmd "synth_design -top $g_top_module -part $g_part_name -rtl -rtl_skip_ip -rtl_skip_constraints"
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set synth_cmd [concat $synth_cmd $vdef_args]
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set synth_cmd [concat $synth_cmd $incdir_args]
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set synth_cmd [concat $synth_cmd $args]
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puts "BUILDER: Checking syntax and elaborating design"
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eval $synth_cmd
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}
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# ---------------------------------------------------
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# Generate post synthesis reports and checkpoint
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# ---------------------------------------------------
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proc ::vivado_utils::generate_post_synth_reports {} {
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variable g_output_dir
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puts "BUILDER: Writing post-synthesis checkpoint"
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write_checkpoint -force $g_output_dir/post_synth
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puts "BUILDER: Writing post-synthesis reports"
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report_utilization -file $g_output_dir/post_synth_util.rpt
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report_utilization -hierarchical -file $g_output_dir/post_synth_util_hier.rpt
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report_drc -ruledeck methodology_checks -file $g_output_dir/methodology.rpt
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report_high_fanout_nets -file $g_output_dir/high_fanout_nets.rpt
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}
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# ---------------------------------------------------
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# Generate post placement reports and checkpoint
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# ---------------------------------------------------
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proc ::vivado_utils::generate_post_place_reports {} {
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variable g_output_dir
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puts "BUILDER: Writing post-placement checkpoint"
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write_checkpoint -force $g_output_dir/post_place
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puts "BUILDER: Writing post-placement reports"
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report_clock_utilization -file $g_output_dir/clock_util.rpt
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report_utilization -file $g_output_dir/post_place_util.rpt
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report_utilization -hierarchical -file $g_output_dir/post_place_util_hier.rpt
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report_timing -sort_by group -max_paths 5 -path_type summary -file $g_output_dir/post_place_timing.rpt
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}
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# ---------------------------------------------------
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# Generate post route reports and checkpoint
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# ---------------------------------------------------
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proc ::vivado_utils::generate_post_route_reports {} {
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variable g_output_dir
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puts "BUILDER: Writing post-route checkpoint"
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write_checkpoint -force $g_output_dir/post_route
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puts "BUILDER: Writing post-route reports"
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if {[file exists "$g_output_dir/clock_util.rpt"] == 0} {
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report_clock_utilization -file $g_output_dir/clock_util.rpt
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}
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report_timing_summary -file $g_output_dir/post_route_timing_summary.rpt
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report_utilization -file $g_output_dir/post_route_util.rpt
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report_utilization -hierarchical -file $g_output_dir/post_route_util_hier.rpt
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report_power -file $g_output_dir/post_route_power.rpt
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report_drc -file $g_output_dir/post_imp_drc.rpt
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report_timing -sort_by group -max_paths 10 -path_type summary -file $g_output_dir/post_route_timing.rpt
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}
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# ---------------------------------------------------
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# Export implementation
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# ---------------------------------------------------
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proc ::vivado_utils::write_implementation_outputs { {byte_swap_bin 0} } {
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variable g_output_dir
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variable g_top_module
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variable g_tools_dir
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puts "BUILDER: Writing implementation netlist and XDC"
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write_verilog -force $g_output_dir/${g_top_module}_impl_netlist.v
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write_xdc -no_fixed_only -force $g_output_dir/${g_top_module}_impl.xdc
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puts "BUILDER: Writing bitfile"
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write_bitstream -force $g_output_dir/${g_top_module}.bit
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puts "BUILDER: Writing config bitstream"
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set binsize [expr [file size $g_output_dir/${g_top_module}.bit]/(1024*1024)]
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set binsize_pow2 [expr {int(pow(2,ceil(log($binsize)/log(2))))}]
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set bin_iface [expr $byte_swap_bin?"SMAPx32":"SMAPx8"]
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write_cfgmem -force -quiet -interface $bin_iface -format BIN -size $binsize_pow2 -disablebitswap -loadbit "up 0x0 $g_output_dir/${g_top_module}.bit" $g_output_dir/${g_top_module}.bin
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puts "BUILDER: Writing debug probes"
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write_debug_probes -force $g_output_dir/${g_top_module}.ltx
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puts "BUILDER: Writing export report"
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report_utilization -omit_locs -file $g_output_dir/build.rpt
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report_timing_summary -no_detailed_paths -file $g_output_dir/build.rpt -append
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if {! [string match -nocase {*timing constraints are met*} [read [open $g_output_dir/build.rpt]]]} {
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send_msg_id {Builder 0-0} error "The design did not satisfy timing constraints. (Implementation outputs were still generated)"
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}
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}
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proc ::vivado_utils::write_netlist_outputs { {suffix ""} } {
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variable g_output_dir
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variable g_top_module
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puts "BUILDER: Writing EDIF netlist and XDC"
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set filename ${g_output_dir}/${g_top_module}
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if { [expr [string length $suffix] > 0] } {
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set filename ${filename}_${suffix}
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}
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write_edif -force ${filename}.edf
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write_xdc -no_fixed_only -force ${filename}.xdc
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puts "BUILDER: Writing export report"
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report_utilization -omit_locs -file $g_output_dir/build.rpt
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report_timing_summary -no_detailed_paths -file $g_output_dir/build.rpt -append
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if {! [string match -nocase {*timing constraints are met*} [read [open $g_output_dir/build.rpt]]]} {
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send_msg_id {Builder 0-0} error "The design did not meet all timing constraints. (Implementation outputs were still generated)"
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}
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}
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# ---------------------------------------------------
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# Close project
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# ---------------------------------------------------
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proc ::vivado_utils::close_batch_project {} {
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variable g_vivado_mode
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if [string equal $g_vivado_mode "batch"] {
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puts "BUILDER: Closing project"
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close_project
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} else {
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puts "BUILDER: In GUI mode. Leaving project open."
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}
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}
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# ---------------------------------------------------
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# Get state variables
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# ---------------------------------------------------
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proc ::vivado_utils::get_top_module {} {
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variable g_top_module
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return $g_top_module
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}
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proc ::vivado_utils::get_part_name {} {
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variable g_part_name
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return $g_part_name
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}
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proc ::vivado_utils::get_vivado_mode {} {
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variable g_vivado_mode
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return $g_vivado_mode
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}
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