43 lines
791 B
Systemverilog
43 lines
791 B
Systemverilog
//
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// Copyright 2024 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Interface: ctrlport_if
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//
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// Description:
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//
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// Defines a SystemVerilog interface for the control-port bus.
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//
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interface ctrlport_if (
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input logic clk,
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input logic rst = 1'b0
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);
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import ctrlport_pkg::*;
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// Consisting of a request and a response moving in different directions.
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ctrlport_request_t req;
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ctrlport_response_t resp;
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// Master driving the request and consuming the response.
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modport master (
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input clk,
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input rst,
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output req,
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input resp
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);
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// Slave consuming the request and driving the response.
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modport slave (
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input clk,
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input rst,
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input req,
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output resp
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);
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endinterface : ctrlport_if
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