317 lines
12 KiB
Python
317 lines
12 KiB
Python
#!/usr/bin/env python3
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#
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# Copyright 2018 Ettus Research, a National Instruments Company
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#
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# SPDX-License-Identifier: GPL-3.0-or-later
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#
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"""
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Container for the list of image package targets, and the information about them
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"""
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PACKAGE_MAPPING = {
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"e310_sg1": {
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"type": "e3xx",
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"package_name": "e3xx_e310_sg1_fpga_default-g{}.zip",
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"files": ['usrp_e310_sg1_fpga.bit',
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'usrp_e310_sg1_fpga.bit.md5',
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'usrp_e310_sg1_fpga.dts',
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'usrp_e310_sg1_fpga.dts.md5',
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'usrp_e310_sg1_fpga.rpt',
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'usrp_e310_sg1_idle_fpga.bit',
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'usrp_e310_sg1_idle_fpga.bit.md5',
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'usrp_e310_sg1_idle_fpga.dts',
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'usrp_e310_sg1_idle_fpga.dts.md5',
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'usrp_e310_sg1_idle_fpga.rpt']
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},
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"e310_sg3": {
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"type": "e3xx",
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"package_name": "e3xx_e310_sg3_fpga_default-g{}.zip",
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"files": ['usrp_e310_sg3_fpga.bit',
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'usrp_e310_sg3_fpga.bit.md5',
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'usrp_e310_sg3_fpga.dts',
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'usrp_e310_sg3_fpga.dts.md5',
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'usrp_e310_sg3_fpga.rpt',
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'usrp_e310_sg3_idle_fpga.bit',
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'usrp_e310_sg3_idle_fpga.bit.md5',
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'usrp_e310_sg3_idle_fpga.dts',
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'usrp_e310_sg3_idle_fpga.dts.md5',
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'usrp_e310_sg3_idle_fpga.rpt']
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},
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"e320": {
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"type": "e3xx",
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"package_name": "e3xx_e320_fpga_default-g{}.zip",
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"files": ['usrp_e320_fpga_1G.bit',
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'usrp_e320_fpga_1G.bit.md5',
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'usrp_e320_fpga_1G.dts',
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'usrp_e320_fpga_1G.dts.md5',
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'usrp_e320_fpga_1G.rpt',
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'usrp_e320_fpga_XG.bit',
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'usrp_e320_fpga_XG.bit.md5',
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'usrp_e320_fpga_XG.dts',
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'usrp_e320_fpga_XG.dts.md5',
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'usrp_e320_fpga_XG.rpt',
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'usrp_e320_fpga_AA.bit',
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'usrp_e320_fpga_AA.bit.md5',
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'usrp_e320_fpga_AA.dts',
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'usrp_e320_fpga_AA.dts.md5',
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'usrp_e320_fpga_AA.rpt']
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},
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"x300": {
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"type": "x3xx",
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"package_name": "x3xx_x300_fpga_default-g{}.zip",
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"files": ["usrp_x300_fpga_HG.lvbitx",
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"usrp_x300_fpga_XG.lvbitx",
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"usrp_x300_fpga_HG.bit",
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"usrp_x300_fpga_HG.rpt",
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"usrp_x300_fpga_XG.bit",
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"usrp_x300_fpga_XG.rpt"]
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},
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"x310": {
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"type": "x3xx",
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"package_name": "x3xx_x310_fpga_default-g{}.zip",
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"files": ["usrp_x310_fpga_HG.lvbitx",
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"usrp_x310_fpga_XG.lvbitx",
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"usrp_x310_fpga_HG.bit",
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"usrp_x310_fpga_HG.rpt",
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"usrp_x310_fpga_XG.bit",
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"usrp_x310_fpga_XG.rpt"]
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},
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"x410": {
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"type": "x4xx",
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"package_name": "x4xx_x410_fpga_default-g{}.zip",
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"files": ["usrp_x410_fpga_X4_200.bit",
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"usrp_x410_fpga_X4_200.bit.md5",
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"usrp_x410_fpga_X4_200.dts",
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"usrp_x410_fpga_X4_200.dts.md5",
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"usrp_x410_fpga_X4_200.rpt",
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"usrp_x410_fpga_CG_400.bit",
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"usrp_x410_fpga_CG_400.bit.md5",
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"usrp_x410_fpga_CG_400.dts",
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"usrp_x410_fpga_CG_400.dts.md5",
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"usrp_x410_fpga_CG_400.rpt",
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]
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},
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"x410_cpld": {
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"type": "x4xx",
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"package_name": "x4xx_x410_cpld_default-g{}.zip",
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"files": ["usrp_x410_cpld_10m04.rpd",
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"usrp_x410_cpld_10m04.rpd.md5",
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"usrp_x410_cpld_10m04.svf",
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"usrp_x410_cpld_10m04.svf.md5",
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"usrp_x410_cpld_10m08.rpd",
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"usrp_x410_cpld_10m08.rpd.md5",
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"usrp_x410_cpld_10m08.svf",
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"usrp_x410_cpld_10m08.svf.md5"]
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},
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"zbx_cpld": {
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"type": "x4xx",
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"package_name": "x4xx_zbx_cpld_default-g{}.zip",
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"files": ["usrp_zbx_cpld.rpd",
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"usrp_zbx_cpld.rpd.md5",
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"usrp_zbx_cpld.svf",
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"usrp_zbx_cpld.svf.md5"]
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},
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"n310": {
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"type": "n3xx",
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"package_name": "n3xx_n310_fpga_default-g{}.zip",
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"files": ['usrp_n310_fpga_HG.bit',
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'usrp_n310_fpga_HG.bit.md5',
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'usrp_n310_fpga_HG.dts',
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'usrp_n310_fpga_HG.dts.md5',
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'usrp_n310_fpga_HG.rpt',
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'usrp_n310_fpga_XG.bit',
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'usrp_n310_fpga_XG.bit.md5',
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'usrp_n310_fpga_XG.dts',
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'usrp_n310_fpga_XG.dts.md5',
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'usrp_n310_fpga_XG.rpt',
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'usrp_n310_fpga_WX.bit',
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'usrp_n310_fpga_WX.bit.md5',
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'usrp_n310_fpga_WX.dts',
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'usrp_n310_fpga_WX.dts.md5',
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'usrp_n310_fpga_WX.rpt',
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'usrp_n310_fpga_AA.bit',
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'usrp_n310_fpga_AA.bit.md5',
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'usrp_n310_fpga_AA.dts',
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'usrp_n310_fpga_AA.dts.md5',
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'usrp_n310_fpga_AA.rpt'],
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},
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"n300": {
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"type": "n3xx",
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"package_name": "n3xx_n300_fpga_default-g{}.zip",
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"files": ['usrp_n300_fpga_HG.bit',
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'usrp_n300_fpga_HG.bit.md5',
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'usrp_n300_fpga_HG.dts',
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'usrp_n300_fpga_HG.dts.md5',
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'usrp_n300_fpga_HG.rpt',
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'usrp_n300_fpga_XG.bit',
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'usrp_n300_fpga_XG.bit.md5',
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'usrp_n300_fpga_XG.dts',
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'usrp_n300_fpga_XG.dts.md5',
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'usrp_n300_fpga_XG.rpt',
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'usrp_n300_fpga_WX.bit',
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'usrp_n300_fpga_WX.bit.md5',
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'usrp_n300_fpga_WX.dts',
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'usrp_n300_fpga_WX.dts.md5',
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'usrp_n300_fpga_WX.rpt',
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'usrp_n300_fpga_AA.bit',
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'usrp_n300_fpga_AA.bit.md5',
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'usrp_n300_fpga_AA.dts',
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'usrp_n300_fpga_AA.dts.md5',
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'usrp_n300_fpga_AA.rpt'],
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},
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"n320": {
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"type": "n3xx",
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"package_name": "n3xx_n320_fpga_default-g{}.zip",
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"files": ['usrp_n320_fpga_HG.bit',
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'usrp_n320_fpga_HG.bit.md5',
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'usrp_n320_fpga_HG.dts',
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'usrp_n320_fpga_HG.dts.md5',
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'usrp_n320_fpga_HG.rpt',
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'usrp_n320_fpga_XG.bit',
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'usrp_n320_fpga_XG.bit.md5',
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'usrp_n320_fpga_XG.dts',
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'usrp_n320_fpga_XG.dts.md5',
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'usrp_n320_fpga_XG.rpt',
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'usrp_n320_fpga_XQ.bit',
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'usrp_n320_fpga_XQ.bit.md5',
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'usrp_n320_fpga_XQ.dts',
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'usrp_n320_fpga_XQ.dts.md5',
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'usrp_n320_fpga_XQ.rpt',
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'usrp_n320_fpga_WX.bit',
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'usrp_n320_fpga_WX.bit.md5',
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'usrp_n320_fpga_WX.dts',
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'usrp_n320_fpga_WX.dts.md5',
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'usrp_n320_fpga_WX.rpt',
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'usrp_n320_fpga_AQ.bit',
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'usrp_n320_fpga_AQ.bit.md5',
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'usrp_n320_fpga_AQ.dts',
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'usrp_n320_fpga_AQ.dts.md5',
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'usrp_n320_fpga_AQ.rpt',
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'usrp_n320_fpga_AA.bit',
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'usrp_n320_fpga_AA.bit.md5',
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'usrp_n320_fpga_AA.dts',
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'usrp_n320_fpga_AA.dts.md5',
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'usrp_n320_fpga_AA.rpt',],
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},
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"n320_cpld": {
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"type": "n3xx",
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"package_name": "n3xx_n320_cpld_default-g{}.zip",
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"files": ['usrp_n320_rh_cpld.svf']
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},
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"n310_cpld": {
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"type": "n3xx",
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"package_name": "n3xx_n310_cpld_default-g{}.zip",
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"files": ['usrp_n310_mg_cpld.svf']
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},
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'n200': {
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'type': 'usrp2',
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'package_name': 'usrp2_n200_fpga_default-g{}.zip',
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'files': ["usrp_n200_r2_fpga.bin",
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"usrp_n200_r3_fpga.bin",
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"usrp_n200_r4_fpga.bin",
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"bit/usrp_n200_r3_fpga.bit",
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"bit/usrp_n200_r4_fpga.bit"],
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},
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'n210': {
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'type': 'usrp2',
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'package_name': 'usrp2_n210_fpga_default-g{}.zip',
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'files': ["usrp_n210_r2_fpga.bin",
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"usrp_n210_r3_fpga.bin",
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"usrp_n210_r4_fpga.bin",
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"bit/usrp_n210_r3_fpga.bit",
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"bit/usrp_n210_r4_fpga.bit"],
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},
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'n200_fw': {
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'type': 'usrp2',
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'package_name': 'usrp2_n200_fw_default-g{}.zip',
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'files': ["usrp_n200_fw.bin"],
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},
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'n210_fw': {
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'type': 'usrp2',
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'package_name': 'usrp2_n210_fw_default-g{}.zip',
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'files': ["usrp_n210_fw.bin"],
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},
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'usrp2': {
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'type': 'usrp2',
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'package_name': 'usrp2_usrp2_fpga_default-g{}.zip',
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'files': ["usrp2_fpga.bin"],
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},
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'usrp2_fw': {
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'type': 'usrp2',
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'package_name': 'usrp2_usrp2_fw_default-g{}.zip',
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'files': ["usrp2_fw.bin"],
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},
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'b200': {
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'type': 'b2xx',
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'package_name': 'b2xx_b200_fpga_default-g{}.zip',
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'files': ["usrp_b200_fpga.bin",
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"usrp_b200_fpga.rpt",],
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},
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'b200mini': {
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'type': 'b2xx',
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'package_name': 'b2xx_b200mini_fpga_default-g{}.zip',
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'files': ["usrp_b200mini_fpga.bin",
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"usrp_b200mini_fpga.rpt",],
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},
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'b205mini': {
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'type': 'b2xx',
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'package_name': 'b2xx_b205mini_fpga_default-g{}.zip',
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'files': ["usrp_b205mini_fpga.bin",
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"usrp_b205mini_fpga.rpt",],
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},
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'b210': {
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'type': 'b2xx',
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'package_name': 'b2xx_b210_fpga_default-g{}.zip',
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'files': ["usrp_b210_fpga.bin",
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"usrp_b210_fpga.rpt",],
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},
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'b2xx_fw': {
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'type': 'b2xx',
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'package_name': 'b2xx_common_fw_default-g{}.zip',
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'files': ["usrp_b200_fw.hex",
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"usrp_b200_bl.img"],
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},
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'b100': {
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'type': 'usrp1',
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'package_name': 'usrp1_b100_fpga_default-g{}.zip',
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'files': ["usrp_b100_fpga_2rx.bin",
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"usrp_b100_fpga.bin"],
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},
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'b100_fw': {
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'type': 'usrp1',
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'package_name': 'usrp1_b100_fw_default-g{}.zip',
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'files': ["usrp_b100_fw.ihx"],
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},
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'usrp1': {
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'type': 'usrp1',
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'package_name': 'usrp1_usrp1_fpga_default-g{}.zip',
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'files': ["usrp1_fpga_4rx.rbf",
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"usrp1_fpga.rbf",
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"usrp1_fw.ihx"],
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},
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'octoclock': {
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'type': 'octoclock',
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'package_name': 'octoclock_octoclock_fw_default-g{}.zip',
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'files': ["octoclock_bootloader.hex",
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"octoclock_r4_fw.hex"],
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},
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'winusb_drv': {
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'type': 'usb',
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'package_name': 'usb_common_windrv_default-g{}.zip',
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'files': ["winusb_driver/",
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"winusb_driver/erllc_uhd_b205mini.inf",
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"winusb_driver/erllc_uhd_b100.inf",
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"winusb_driver/erllc_uhd_b200_reinit.inf",
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"winusb_driver/erllc_uhd_b200mini.inf",
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"winusb_driver/erllc_uhd_b200.inf",
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"winusb_driver/amd64/",
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"winusb_driver/amd64/WdfCoInstaller01009.dll",
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"winusb_driver/amd64/winusbcoinstaller2.dll",
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"winusb_driver/x86/",
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"winusb_driver/x86/WdfCoInstaller01009.dll",
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"winusb_driver/x86/winusbcoinstaller2.dll",
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"winusb_driver/erllc_uhd_usrp1.inf",
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"winusb_driver/erllc_uhd_makecat.cdf",
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"winusb_driver/erllc_uhd.cat"],
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},
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}
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