adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
92 lines
2.7 KiB
Makefile
92 lines
2.7 KiB
Makefile
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir.
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BASE_DIR = ../../..
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynquplusRFSOC
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PART_ID = xczu28dr/ffvg1517/-1/e
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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)
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include ../common/Makefile.srcs
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include ../100m/Makefile.srcs
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include ../200m/Makefile.srcs
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include ../400m/Makefile.srcs
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DESIGN_SRCS += $(abspath \
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../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd \
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$(RF_COMMON_SRCS) \
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$(RF_X410_SRCS) \
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$(RF_100M_SRCS) \
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$(RF_200M_SRCS) \
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$(RF_400M_SRCS) \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = $(BASE_DIR)/x400/ip
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LIB_IP_DIR = $(BASE_DIR)/../lib/ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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#
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# These TBs don't use any IP yet :)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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include $(BASE_DIR)/../sim/general/Makefile.srcs
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# Define only one top-level module
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SIM_TOP = rf_all_tb
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# Simulation runtime in microseconds
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SIM_RUNTIME_US = 1000
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SIM_SRCS = \
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$(abspath tb_adc_gearbox_2x1.vhd ) \
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$(abspath tb_adc_gearbox_2x4.vhd ) \
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$(abspath tb_adc_gearbox_8x4.vhd ) \
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$(abspath tb_capture_sysref.vhd ) \
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$(abspath tb_dac_gearbox_12x8.vhd ) \
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$(abspath tb_dac_gearbox_4x2.vhd ) \
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$(abspath tb_dac_gearbox_6x12.vhd ) \
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$(abspath tb_ddc_400m_saturate.vhd ) \
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$(abspath tb_duc_400m_saturate.vhd ) \
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$(abspath tb_rf_nco_reset.vhd ) \
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$(abspath tb_x410_rf_reset_controller.vhd ) \
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$(abspath rf_all_tb.sv ) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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