adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
131 lines
3.6 KiB
Makefile
131 lines
3.6 KiB
Makefile
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(IP_DIR)/xge_pcs_pma/Makefile.inc
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include $(IP_DIR)/axi_interconnect_app_bd/Makefile.inc
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include $(IP_DIR)/axi_interconnect_eth_bd/Makefile.inc
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include $(IP_DIR)/axi_interconnect_dma_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_1x64_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_2x64_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_4x64_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_1x128_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_2x128_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_4x128_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_1x512_512_bd/Makefile.inc
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include $(IP_DIR)/axi_inter_2x512_512_bd/Makefile.inc
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include $(IP_DIR)/axi64_4k_2clk_fifo/Makefile.inc
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
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include $(IP_DIR)/eth_100g_bd/Makefile.inc
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include $(IP_DIR)/axi_eth_dma_bd/Makefile.inc
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include $(IP_DIR)/hb47_1to2/Makefile.inc
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include $(IP_DIR)/hb47_2to1/Makefile.inc
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ifdef X410
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include $(IP_DIR)/ddr4_64bits/Makefile.inc
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include $(IP_DIR)/adc_100m_bd/Makefile.inc
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include $(IP_DIR)/adc_400m_bd/Makefile.inc
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include $(IP_DIR)/dac_100m_bd/Makefile.inc
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include $(IP_DIR)/dac_400m_bd/Makefile.inc
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include $(IP_DIR)/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/Makefile.inc
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endif
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BD_SRCS = \
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$(IP_X4XX_PS_RFDC_BD_SRCS) \
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$(IP_X4XX_PS_RFDC_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_APP_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_BD_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
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$(IP_AXI_INTER_1X64_512_BD_SRCS) \
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$(IP_AXI_INTER_2X64_512_BD_SRCS) \
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$(IP_AXI_INTER_4X64_512_BD_SRCS) \
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$(IP_AXI_INTER_1X128_512_BD_SRCS) \
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$(IP_AXI_INTER_2X128_512_BD_SRCS) \
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$(IP_AXI_INTER_4X128_512_BD_SRCS) \
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$(IP_AXI_INTER_1X512_512_BD_SRCS) \
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$(IP_AXI_INTER_2X512_512_BD_SRCS) \
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$(IP_100G_BD_SRCS) \
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$(IP_100G_HDL_SRCS) \
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$(IP_AXI_ETH_DMA_BD_SRCS) \
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$(IP_AXI_ETH_DMA_BD_HDL_SRCS)
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ifdef X410
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BD_SRCS += \
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$(IP_ADC_100M_BD_SRCS) \
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$(IP_ADC_100M_HDL_SRCS) \
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$(IP_DAC_100M_BD_SRCS) \
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$(IP_DAC_100M_HDL_SRCS) \
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$(IP_ADC_400M_BD_SRCS) \
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$(IP_ADC_400M_HDL_SRCS) \
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$(IP_DAC_400M_BD_SRCS) \
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$(IP_DAC_400M_HDL_SRCS)
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endif
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IP_XCI_SRCS = \
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$(IP_XGE_PCS_PMA_SRCS) \
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$(IP_AXI64_4K_2CLK_FIFO_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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$(IP_FIFO_4K_2CLK_SRCS) \
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$(IP_HB47_1TO2_SRCS) \
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$(IP_HB47_2TO1_SRCS) \
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ifdef X410
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IP_XCI_SRCS += \
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$(IP_DDR4_64BITS_SRCS)
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endif
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BD_OUTPUTS = \
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$(BD_X4XX_PS_RFDC_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_APP_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_ETH_BD_OUTS) \
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$(BD_AXI_INTERCONNECT_DMA_BD_OUTS) \
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$(BD_AXI_INTER_1x64_512_BD_OUTS) \
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$(BD_AXI_INTER_2x64_512_BD_OUTS) \
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$(BD_AXI_INTER_4x64_512_BD_OUTS) \
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$(BD_AXI_INTER_1X128_512_BD_OUTS) \
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$(BD_AXI_INTER_2X128_512_BD_OUTS) \
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$(BD_AXI_INTER_4x128_512_BD_OUTS) \
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$(BD_AXI_INTER_1X512_512_BD_OUTS) \
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$(BD_AXI_INTER_2X512_512_BD_OUTS) \
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$(BD_100G_BD_OUTS) \
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$(BD_AXI_ETH_DMA_BD_OUTS)
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ifdef X410
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BD_OUTPUTS += \
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$(BD_ADC_100M_BD_OUTS) \
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$(BD_ADC_400M_BD_OUTS) \
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$(BD_DAC_100M_BD_OUTS) \
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$(BD_DAC_400M_BD_OUTS)
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endif
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IP_SYNTH_OUTPUTS = \
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$(IP_XGE_PCS_PMA_OUTS) \
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$(IP_AXI64_4K_2CLK_FIFO_OUTS) \
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$(IP_FIFO_SHORT_2CLK_OUTS) \
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$(IP_FIFO_4K_2CLK_OUTS) \
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$(IP_HB47_1TO2_OUTS) \
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$(IP_HB47_2TO1_OUTS) \
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ifdef X410
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IP_SYNTH_OUTPUTS += \
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$(IP_DDR4_64BITS_OUTS)
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endif
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IP_HDL_SIM_SRCS = \
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$(IP_AXI64_4K_2CLK_FIFO_HDL_SIM_SRCS) \
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$(IP_FIFO_4K_2CLK_HDL_SIM_SRCS) \
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$(IP_FIFO_SHORT_2CLK_HDL_SIM_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SIM_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_HDL_SIM_SRCS) \
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$(IP_100G_HDL_SIM_SRCS) \
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$(IP_XGE_PCS_PMA_HDL_SIM_SRCS)
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ip: $(IP_SYNTH_OUTPUTS) $(BD_OUTPUTS)
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.PHONY: ip
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