b210-k7-fpga

Files

T

Ashish Chaudhari adf2da6ac7 fpga: Multiple X300 FPGA bugfixes and enhancements

- Fixed 10GigE firmware communication issues and sequence errors for TX
- Multiple changes to help ease timing closure
- Cleaned up build scripts
- Switched to Xilinx ISE 14.7 as the default build tool for X300


Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0

2014-09-24 18:45:31 -07:00

gtx

fpga: Multiple X300 FPGA bugfixes and enhancements

2014-09-24 18:45:31 -07:00

README

fpga: Multiple X300 FPGA bugfixes and enhancements

2014-09-24 18:45:31 -07:00

ten_gig_eth_pcs_pma_block.v

fpga: Multiple X300 FPGA bugfixes and enhancements

2014-09-24 18:45:31 -07:00

ten_gig_eth_pcs_pma_mod.v

fpga: Multiple X300 FPGA bugfixes and enhancements

2014-09-24 18:45:31 -07:00

ten_gig_eth_pcs_pma_x300_top.ucf

fpga: Multiple X300 FPGA bugfixes and enhancements

2014-09-24 18:45:31 -07:00

ten_gig_eth_pcs_pma_x300_top.v

fpga: Multiple X300 FPGA bugfixes and enhancements

2014-09-24 18:45:31 -07:00

README

The files in this directory have been adapted from the "Ten Gigabit EthernetPCS/PMA or SGMII (10GBASE-R/KR)" Xilinx IPCore example design.