99 lines
2.7 KiB
Verilog
99 lines
2.7 KiB
Verilog
module radio_tb();
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//
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// Pull in standard tasks and signal name declarations.
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//
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`include "task_libraray.v"
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//
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// DUT
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//
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radio radio_i0
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#(
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.CHIPSCOPE (0),
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.DELETE_DSP(0))
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(
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.radio_clk(clk),
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.radio_clk_2x(1'b0), // Unused
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.radio_rst(reset),
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.rx(rx),
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.tx(tx),
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.db_gpio(db_gpio),
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.fp_gpio(fp_gpio),
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.sen(sen),
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.sclk(sclk),
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.mosi(mosi),
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.miso(miso),
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.misc_outs(misc_outs),
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.leds(leds),
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.bus_clk(clk),
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.bus_rst(reset),
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.in_tdata(data_in),
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.in_tlast(last_in),
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.in_tvalid(valid_in),
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.in_tready(ready_in),
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.out_tdata(data_out),
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.out_tlast(data_out),
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.out_tvalid(valid_out),
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.out_tready(ready_out),
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.tx_tdata_bi(tx_tdata_bi),
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.tx_tlast_bi(tx_tlast_bi),
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.tx_tvalid_bi(tx_tvalid_bi),
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.tx_tready_bi(tx_tready_bi),
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.tx_tdata_bo(tx_tdata_bo),
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.tx_tlast_bo(tx_tlast_bo),
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.tx_tvalid_bo(tx_tvalid_bo),
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.tx_tready_bo(tx_tready_bo),
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.pps(pps),
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.debug()
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);
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//
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// Alternate smaller internal SRAM based FIFO's for Tx when DRAM not compiled into FPGA.
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//
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wire [63:0] tx_tdata_0; wire tx_tlast_0, tx_tvalid_0, tx_tready_0;
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wire [63:0] tx_tdata_1; wire tx_tlast_1, tx_tvalid_1, tx_tready_1;
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wire [63:0] tx_tdata_2; wire tx_tlast_2, tx_tvalid_2, tx_tready_2;
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axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_0
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({tx_tlast_bo,tx_tdata_bo}), .i_tvalid(tx_tvalid_bo), .i_tready(tx_tready_bo),
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.o_tdata({tx_tlast_0,tx_tdata_0}), .o_tvalid(tx_tvalid_0), .o_tready(tx_tready_0),
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.space(), .occupied());
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axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_1
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({tx_tlast_0,tx_tdata_0}), .i_tvalid(tx_tvalid_0), .i_tready(tx_tready_0),
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.o_tdata({tx_tlast_1,tx_tdata_1}), .o_tvalid(tx_tvalid_1), .o_tready(tx_tready_1),
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.space(), .occupied());
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axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_2
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({tx_tlast_1,tx_tdata_1}), .i_tvalid(tx_tvalid_1), .i_tready(tx_tready_1),
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.o_tdata({tx_tlast_2,tx_tdata_2}), .o_tvalid(tx_tvalid_2), .o_tready(tx_tready_2),
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.space(), .occupied());
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axi_fifo #(.WIDTH(65), .SIZE(`SRAM_FIFO_SIZE-2)) tx_fifo0_3
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i_tdata({tx_tlast_2,tx_tdata_2}), .i_tvalid(tx_tvalid_2), .i_tready(tx_tready_2),
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.o_tdata({tx_tlast_bi,tx_tdata_bi}), .o_tvalid(tx_tvalid_bi), .o_tready(tx_tready_bi),
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.space(), .occupied());
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//
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// DUT ends.
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//
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//
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// Include per simulation scripts
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//
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`include "simulation_script.v"
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endmodule // radio_tb
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