61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
32 lines
1.3 KiB
Systemverilog
32 lines
1.3 KiB
Systemverilog
//
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// Copyright 2021 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: radio_ctrlport_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// DB_WINDOW : 0x0 (rfdc_timing_control.v)
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// RFDC_TIMING_WINDOW : 0x8000 (rfdc_timing_control.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group RADIO_CTRLPORT_WINDOWS
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//===============================================================================
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// DB_WINDOW Window (from rfdc_timing_control.v)
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localparam DB_WINDOW = 'h0; // Window Offset
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localparam DB_WINDOW_SIZE = 'h8000; // size in bytes
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// RFDC_TIMING_WINDOW Window (from rfdc_timing_control.v)
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localparam RFDC_TIMING_WINDOW = 'h8000; // Window Offset
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localparam RFDC_TIMING_WINDOW_SIZE = 'h8000; // size in bytes
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