Max Köhler
6bea1f8222
This changes the for loop to use the generate keyword, making it compatible with Verilog 2001. This allows tools that only support Verilog 2001 to use this file (e.g., Intel Quartus). Original-commit: b92597e1c9b6f09d5e62e55a60e33c04d437a50a
171 lines
6.4 KiB
Verilog
171 lines
6.4 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_decoder_param
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//
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// Description:
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//
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// This block splits a single control port interface into multiple. It is
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// used when you have a single master that needs to access multiple slaves.
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// For example, a NoC block where the registers are implemented in multiple
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// submodules that must be read/written by a single NoC shell.
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//
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// This version also implements address decoding. The request is passed to a
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// slave only if the address falls within that slave's address space. Each
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// slave can have a unique base address and address space size. The address
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// space is broken up as follows.
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//
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// PORT_BASE[0*20 +: 20] = Port 0 base address
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// │ ┐
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// │ ├── 2**PORT_ADDR_W[0*32 +: 32] bytes for slave 0
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// │ ┘
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// .
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// .
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// PORT_BASE[1*20 +: 20] = Port 1 base address
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// │ ┐
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// │ ├── 2**PORT_ADDR_W[1*32 +: 32] bytes for slave 1
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// │ ┘
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// .
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// .
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//
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// When passed to the slave, the base address is stripped from the request
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// address so that only the PORT_ADDR_W-bit address is passed through.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves to connect to a master.
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//
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// PORT_BASE : Base addresses to use fore each slave. This is a
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// concatenation of 20-bit addresses, where the right-most
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// (least-significant) 20 bits corresponds to slave 0. Each
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// address must be a multiple of 2**PORT_ADDR_W, where
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// PORT_ADDR_W is the number of address bits allocated to that
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// slave.
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//
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// PORT_ADDR_W : Number of address bits to allocate to each slave. This is a
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// concatenation of 32-bit integers, where the right-most
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// (least-significant) 32 bits corresponds to the address space
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// for slave 0.
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//
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module ctrlport_decoder_param #(
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parameter NUM_SLAVES = 4,
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parameter PORT_BASE = { 20'h300, 20'h200, 20'h100, 20'h000 },
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parameter PORT_ADDR_W = { 32'd8, 32'd8, 32'd8, 32'd8 }
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Slave Interface
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status,
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output reg [31:0] s_ctrlport_resp_data,
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// Master Interfaces
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output reg [ NUM_SLAVES-1:0] m_ctrlport_req_wr = 0,
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output reg [ NUM_SLAVES-1:0] m_ctrlport_req_rd = 0,
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output reg [20*NUM_SLAVES-1:0] m_ctrlport_req_addr = 0,
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output reg [32*NUM_SLAVES-1:0] m_ctrlport_req_data,
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output reg [ 4*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
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output reg [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
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output reg [64*NUM_SLAVES-1:0] m_ctrlport_req_time,
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input wire [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
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input wire [ 2*NUM_SLAVES-1:0] m_ctrlport_resp_status,
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input wire [32*NUM_SLAVES-1:0] m_ctrlport_resp_data
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);
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//---------------------------------------------------------------------------
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// Address Decode Logic
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//---------------------------------------------------------------------------
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//
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// Check if the upper bits of the request address match each slave. If the
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// address matches, set the corresponding dec_mask[] bit.
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//
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//---------------------------------------------------------------------------
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wire [NUM_SLAVES-1:0] dec_mask; // Address decoder mask
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generate
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genvar i;
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for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_dec_mask
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localparam [19:0] BASE_ADDR = PORT_BASE [i*20 +: 20];
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localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];
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assign dec_mask[i] = ~|((s_ctrlport_req_addr ^ BASE_ADDR) & ((~0) << ADDR_W));
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end
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//---------------------------------------------------------------------------
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// Split the requests among the slaves
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//---------------------------------------------------------------------------
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for (i = 0; i < NUM_SLAVES; i = i+1) begin : gen_split
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localparam [31:0] ADDR_W = PORT_ADDR_W[i*32 +: 32];
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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m_ctrlport_req_wr[i] <= 1'b0;
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m_ctrlport_req_rd[i] <= 1'b0;
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end else begin
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// Mask WR and RD based on address decoding
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m_ctrlport_req_wr[i] <= s_ctrlport_req_wr & dec_mask[i];
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m_ctrlport_req_rd[i] <= s_ctrlport_req_rd & dec_mask[i];
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// Other values pass through to all slaves, but should be ignored
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// unless WR or RD is asserted.
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m_ctrlport_req_data [32*i +: 32] <= s_ctrlport_req_data;
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m_ctrlport_req_byte_en [4*i +: 4] <= s_ctrlport_req_byte_en;
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m_ctrlport_req_has_time[i] <= s_ctrlport_req_has_time;
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m_ctrlport_req_time [64*i +: 64] <= s_ctrlport_req_time;
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// Mask the address bits to that of the slaves address space.
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m_ctrlport_req_addr[20*i +: 20] <= 20'b0;
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m_ctrlport_req_addr[20*i +: ADDR_W] <= s_ctrlport_req_addr[ADDR_W-1 : 0];
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end
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end
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end
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endgenerate
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//---------------------------------------------------------------------------
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// Decode the responses
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//---------------------------------------------------------------------------
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reg [31:0] data;
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reg [ 1:0] status;
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reg ack = 0;
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// Take the responses and mask them with ack, then OR them together
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always @(*) begin : comb_decode
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integer s;
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data = 0;
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status = 0;
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ack = 0;
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for (s = 0; s < NUM_SLAVES; s = s+1) begin
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data = data | (m_ctrlport_resp_data [s*32 +: 32] & {32{m_ctrlport_resp_ack[s]}});
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status = status | (m_ctrlport_resp_status[s* 2 +: 2] & { 2{m_ctrlport_resp_ack[s]}});
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ack = ack | m_ctrlport_resp_ack[s];
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end
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end
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// Register the output to break combinatorial path
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack <= 0;
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end else begin
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s_ctrlport_resp_data <= data;
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s_ctrlport_resp_status <= status;
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s_ctrlport_resp_ack <= ack;
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end
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end
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endmodule
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