398 lines
13 KiB
Systemverilog
398 lines
13 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi4s_add_bytes
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//
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// Description:
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//
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// Add zero filled bytes to a packet. TKEEP is ignored. TUSER should have the
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// format {error, trailing bytes};
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//
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// LIMITATIONS
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// The block only adds bytes to the beginning of a word.
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//
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// Parameters:
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//
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// ADD_START - Add bytes before this point (0 means start)
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// 0 is the only supported value right now
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// ADD_BYTES - Number of bytes to add
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// SYNC - When 1 we wait for the start word to be
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// valid before we start shifting.
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// When 0 we aggressively pad 0 early, but
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// it means the extra space may be added before
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// we setup the values we want to overwrite onto
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// that space.
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//
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module axi4s_add_bytes #(
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int ADD_START = 0,
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int ADD_BYTES = 6,
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bit SYNC = 1
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) (
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interface.slave i, // AxiStreamIf or AxiStreamPacketIf
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interface.master o // AxiStreamIf or AxiStreamPacketIf
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);
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localparam BYTES_PER_WORD = i.DATA_WIDTH/8;
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// tUSER - always {error,numbytes}
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localparam UWIDTH = $clog2(BYTES_PER_WORD+1);
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//packet position in bytes of the last removed byte.
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localparam ADD_END = ADD_START + ADD_BYTES-1;
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//packet position in bytes of the 1st byte after removal.
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localparam ADD_RESTART = ADD_END+1;
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////////////// Byte offsets in a word /////////////////
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localparam START_BYTE = ADD_START % BYTES_PER_WORD;
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localparam END_BYTE = ADD_END % BYTES_PER_WORD;
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localparam RESTART_BYTE = ADD_RESTART % BYTES_PER_WORD;
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// An Important shift offset
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localparam BYTE_SHIFT = (BYTES_PER_WORD - RESTART_BYTE)%BYTES_PER_WORD;
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// Subcase Recognition
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// EXACT case - the removal expression is removing an entire word
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localparam EXACT = BYTE_SHIFT == 0;
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`include "axi4s.vh"
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// Parameter Checks
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initial begin
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assert (i.DATA_WIDTH == o.DATA_WIDTH) else
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$fatal(1, "DATA_WIDTH mismatch");
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assert (i.USER_WIDTH == o.USER_WIDTH) else
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$fatal(1, "USER_WIDTH mismatch");
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assert (i.USER_WIDTH >= UWIDTH) else
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$fatal(1, "i.USER_WIDTH is to small");
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assert (o.USER_WIDTH >= UWIDTH) else
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$fatal(1, "o.USER_WIDTH is to small");
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assert (ADD_START == 0) else
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$fatal(1, "Only tested for ADD_START = 0");
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end
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AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
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.TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
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s0(i.clk,i.rst);
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AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
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.TKEEP(0),.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
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s1(i.clk,i.rst);
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// move from AxiStreamIfc to AxiStreamPacketIf
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always_comb begin
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`AXI4S_ASSIGN(s0,i)
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end
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logic reached_start;
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logic reached_end;
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logic byte_overflow;
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logic [i.DATA_WIDTH-1:0] zero_data;
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logic [i.DATA_WIDTH-1:0] last_tdata;
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logic [i.DATA_WIDTH-1:0] remaining_shift_data;
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logic [i.DATA_WIDTH-1:0] last_shift_data;
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logic [i.DATA_WIDTH-1:0] first_shifted_data;
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logic error_bit, error_bit_old;
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// Cache a couple of words from the bus
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always_ff @(posedge s0.clk) begin
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if (s0.rst) begin
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last_tdata <= 0;
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end else if (s0.tvalid && s0.tready) begin
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last_tdata <= s0.tdata;
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end
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end
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if (EXACT) begin
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always_comb begin
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// If END_BYTE=3
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zero_data = 'b0;
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first_shifted_data = s0.tdata;
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remaining_shift_data = s0.tdata;
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last_shift_data = s0.tdata;
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end
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end else begin
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always_comb begin
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zero_data = 'b0;
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// If END_BYTE=2 [7:0] [23:0]
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// If END_BYTE=1 [15:0] [15:0]
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// If END_BYTE=0 [23:0] [7:0]
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first_shifted_data = {s0.tdata[BYTE_SHIFT*8-1:0],zero_data[END_BYTE*8+7:0]};
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// If END_BYTE=0 [23:0] [31:24]
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remaining_shift_data = {s0.tdata[BYTE_SHIFT*8-1:0],last_tdata[s0.DATA_WIDTH-1:BYTE_SHIFT*8]};
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// If END_BYTE=0 [23:0] [31:24]
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last_shift_data = {zero_data[BYTE_SHIFT*8-1:0],s0.tdata[s0.DATA_WIDTH-1:BYTE_SHIFT*8]};
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end
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end
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//-----------------------------------------------------------------------
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// user write function
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// this module ASSUMES user includes error in the MSB and the rest is the
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// number of bytes in the word
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//-----------------------------------------------------------------------
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function automatic [UWIDTH-1:0] uwrite(error=0,[UWIDTH-2:0] bytes=0);
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begin
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return {error,bytes};
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end
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endfunction
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//-----------------------------------------------------------------------
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// get_error -extract error from tuser
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//-----------------------------------------------------------------------
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function automatic get_error([UWIDTH-1:0] tuser);
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begin
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return tuser[UWIDTH-1];
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end
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endfunction
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//-----------------------------------------------------------------------
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// get_bytes -extract num_bytes from tuser
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//-----------------------------------------------------------------------
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function automatic [UWIDTH-1:0] get_bytes([UWIDTH-1:0] tuser);
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logic [UWIDTH-1:0] bytes;
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begin
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if (tuser[UWIDTH-2:0] == 0) bytes = BYTES_PER_WORD;
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else bytes = tuser[UWIDTH-2:0];
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return bytes;
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end
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endfunction
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//---------------------------------------
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// remove state machine
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//---------------------------------------
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typedef enum {ST_PRE_ADD, ST_ADDING, ST_POST_ADD,ST_BONUS} add_state_t;
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add_state_t add_state = ST_PRE_ADD;
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add_state_t next_add_state = ST_PRE_ADD;
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always_ff @(posedge s0.clk) begin
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if (s0.rst) begin
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error_bit_old <= 0;
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end else begin
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// must hold until output completes
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if (s1.tlast && s1.tvalid && s1.tready) begin
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error_bit_old <= 0;
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// but they set based on the input
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end else if (s0.tvalid && s0.tready) begin
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error_bit_old <= error_bit;
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end
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end
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end
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// Find the landmark bytes
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always_comb error_bit = get_error(s0.tuser) || error_bit_old;
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always_comb begin
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reached_start = s1.reached_packet_byte(ADD_START);
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reached_end = s1.reached_packet_byte(ADD_START+ADD_BYTES);
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end
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if (EXACT) begin
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always_comb byte_overflow = 0;
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end else begin
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always_comb byte_overflow = get_bytes(s0.tuser) > BYTE_SHIFT;
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end
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// because s0.tready feeds back and generates a
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// change event for the entire interface,
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// it can trigger an infinite loop of assignment
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// even when nothing is changing. This breaks
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// the feedback loop.
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logic s0_tready;
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always_comb s0.tready = s0_tready;
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// ADD state machine
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always_comb begin
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// default assignment of next_state
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next_add_state = add_state;
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s1.tuser = s0.tuser;
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s1.tlast = s0.tlast;
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s1.tvalid = s0.tvalid;
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s1.tdata = first_shifted_data;
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s0_tready = s1.tready;
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case (add_state)
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// *****************************************************
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// PRE_ADD - wait till we reach ADD_START
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// *****************************************************
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ST_PRE_ADD: begin
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if (!SYNC || s0.tvalid) begin
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// reached start and end in same clock and end of word
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if (reached_start && reached_end && s0.tlast) begin
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// if final word has more bytes than we can fit.
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if (byte_overflow) begin
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s1.tlast = 0;
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s1.tvalid = s0.tvalid;
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s0_tready = 0; // don't advance
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s1.tdata = first_shifted_data;
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s1.tuser = uwrite(error_bit,BYTES_PER_WORD);
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if (s0.tvalid && s1.tready) begin
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next_add_state = ST_BONUS;
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end
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// we can finish this clock because final word
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// didn't overflow into an additional word.
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end else begin
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s1.tlast = 1;
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s1.tvalid = s0.tvalid;
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s0_tready = s1.tready;
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s1.tdata = first_shifted_data;
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s1.tuser = uwrite(error_bit,get_bytes(s0.tuser) + RESTART_BYTE);
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// NO state advance
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end
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// reached start and end, and not the end of the packet
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end else if (reached_start && reached_end && !s0.tlast) begin
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s1.tlast = 0;
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s1.tvalid = s0.tvalid;
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s0_tready = s1.tready;
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s1.tdata = first_shifted_data;
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s1.tuser = uwrite(error_bit,BYTES_PER_WORD);
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if (s0.tvalid && s1.tready) begin
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next_add_state = ST_POST_ADD;
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end
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// reached start but not the end of byte insertion
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end else if (reached_start && !reached_end) begin
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s1.tlast = 0;
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s1.tvalid = 1;
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s0_tready = 0; // don't advance
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s1.tdata = zero_data;
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s1.tuser = uwrite(0,BYTES_PER_WORD);
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if (s1.tready) begin
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next_add_state = ST_ADDING;
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end
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end
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end
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end //ST_PRE_REMOVE
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// *****************************************************
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// REMOVING - burn words until we have data to
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// start sending again
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// *****************************************************
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ST_ADDING: begin
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//defaults
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s1.tlast = 0;
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s1.tvalid = 1;
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s0_tready = 0; // don't advance
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s1.tdata = zero_data;
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s1.tuser = uwrite(0,BYTES_PER_WORD);
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// reached the end of incoming packet and data insertion
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if (reached_end && s0.tlast) begin
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// if final word has more bytes than we can fit.
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if (byte_overflow) begin
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s1.tlast = 0;
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s1.tvalid = s0.tvalid;
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s0_tready = 0; // don't advance
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s1.tdata = first_shifted_data;
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s1.tuser = uwrite(error_bit,BYTES_PER_WORD);
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if (s0.tvalid && s1.tready) begin
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next_add_state = ST_BONUS;
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end
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end else begin
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// we can finish this clock because final word
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// didn't overflow into an additional word.
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s1.tlast = 1;
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s1.tvalid = s0.tvalid;
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s0_tready = s1.tready;
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s1.tdata = first_shifted_data;
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s1.tuser = uwrite(error_bit,get_bytes(s0.tuser) + RESTART_BYTE);
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if (s0.tvalid && s1.tready) begin
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next_add_state = ST_PRE_ADD;
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end
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end
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// reached the end of data insertion - not end of packet
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end else if (reached_end && !s0.tlast) begin
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s1.tlast = 0;
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s1.tvalid = s0.tvalid;
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s0_tready = s1.tready;
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s1.tdata = first_shifted_data;
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s1.tuser = uwrite(error_bit,BYTES_PER_WORD);
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if (s0.tvalid && s1.tready) begin
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next_add_state = ST_POST_ADD;
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end
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end
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end
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// *****************************************************
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// POST_ADD waiting for end
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// *****************************************************
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ST_POST_ADD: begin
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//defaults
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s1.tlast = 0;
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s1.tvalid = s0.tvalid;
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s0_tready = s1.tready;
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s1.tdata = remaining_shift_data;
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s1.tuser = uwrite(error_bit,BYTES_PER_WORD);
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// reached the end, but we have extra bytes to send
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if (s0.tlast && byte_overflow) begin
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s1.tlast = 0;
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s0_tready = 0; // don't let a advance
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if (s0.tvalid && s1.tready) begin
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next_add_state = ST_BONUS;
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end
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// reached the end, and don't need the bonus state
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end else if (s0.tlast) begin
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s1.tlast = 1;
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s1.tuser = uwrite(error_bit,get_bytes(s0.tuser) + RESTART_BYTE);
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if (s1.tready && s0.tvalid) begin
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next_add_state = ST_PRE_ADD;
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end
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end
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end
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// *****************************************************
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// BONUS write out any overflow words
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// *****************************************************
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ST_BONUS: begin
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//defaults
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s1.tdata = last_shift_data;
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s1.tuser = uwrite(error_bit,get_bytes(s0.tuser)+ RESTART_BYTE);
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s1.tlast = 1;
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s1.tvalid = s0.tvalid;
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s0_tready = s1.tready;
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if (s1.tready && s0.tvalid) begin
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next_add_state = ST_PRE_ADD;
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end
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end
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// We should never get here
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default: begin
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next_add_state = ST_PRE_ADD;
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end
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endcase
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end
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always_ff @(posedge s0.clk) begin
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if (s0.rst) begin
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add_state <= ST_PRE_ADD;
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end else begin
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add_state <= next_add_state;
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end
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end
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always_comb begin
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`AXI4S_ASSIGN(o,s1)
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end
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endmodule : axi4s_add_bytes
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