miegl/b210-k7-fpga
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b210-k7-fpga/lib/rfnoc/crossbar
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Wade Fife 37b8b0d017 fpga: rfnoc: Move synthesizable code from sim to lib 
Original-commit: d9f8c08dfb1afe98c35c5911125c6eead869713f
2025-03-17 17:47:16 -05:00
..
chdr_crossbar_nxn_tb
fpga: rfnoc: Move synthesizable code from sim to lib
2025-03-17 17:47:16 -05:00
crossbar_tb
fpga: lib: rfnoc: Support multiple port widths on crossbar
2023-02-24 08:07:17 -06:00
synth
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_ctrl_crossbar_2d_mesh.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_ctrl_crossbar_nxn.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_ingress_vc_buff.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_port_terminator.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_switch.v
fpga: rfnoc: Add labels to axi_switch generate blocks
2021-10-28 23:15:41 -05:00
chdr_crossbar_nxn.v
fpga: lib: Fix Vivado warnings
2023-06-09 09:01:04 -05:00
chdr_xb_ingress_buff.v
fpga: lib: rfnoc: Remove redundant packet gate
2023-02-24 08:07:17 -06:00
chdr_xb_routing_table.v
fpga: rfnoc: Add documentation to chdr_xb_routing_table
2021-10-28 23:15:41 -05:00
gen_node_to_coord_mapping.py
fpga: lib: Fix Vivado warnings
2023-06-09 09:01:04 -05:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mesh_2d_dor_router_multi_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mesh_2d_dor_router_single_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mesh_node_mapping.vh
fpga: lib: Fix Vivado warnings
2023-06-09 09:01:04 -05:00
README.pdf
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
torus_2d_dor_router_multi_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
torus_2d_dor_router_single_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00