michael-west
b8163da1d1
The FIR filter applied gain. Removing it caused incorrect scaling and signals where every other sample was zero. Also parameterized heterodyne frontend processing so it would not use resources in images not requiring it. Signed-off-by: michael-west <michael.west@ettus.com> Original-commit: c27519624ec0f3a44ac1130635a03dafcf2e7f13
335 lines
13 KiB
Verilog
335 lines
13 KiB
Verilog
//
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// Copyright 2015 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rx_frontend_gen3
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//
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// Description:
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//
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// RX Frontend Correction Module
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// -----------------------------
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//
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// This module will perform the following modifications of the signal, in this
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// order:
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//
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// 1) I/Q Swapping/Reordering: The I and Q values from the ADC can be remapped
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// arbitrarily and can be inverted. The behaviour of this IQ mux is
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// controlled by writing to the settings register at SR_IQ_MAPPING.
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//
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// This register uses the following bits:
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//
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// Bit 0: Set to 1 to swap I and Q.
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// Bit 1: Set to 1 to enable real mode. If it is 1, then
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// the Q input signal is ignored and assumed to be zero.
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// Bit 2: Set to 1 to invert the Q input signal
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// Bit 3: Set to 1 to invert the I input signal
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// Bit 4: Set to 1 to enable the quarter-rate downconverter (only relevant
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// when BYPASS_HETERODYNE is set to 0, see below).
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// Bit 7: Disable all corrections in this module.
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//
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// 2) DC offset correction. See the rx_dcoffset module for details. This is
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// either a fixed DC offset, or a notch filter around DC. The behaviour of
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// this correction step is controlled by writing to settings registers at
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// SR_OFFSET_I and SR_OFFSET_Q (they get forwarded to rx_dcoffset).
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// Set BYPASS_DC_OFFSET_CORR to 1 to not synthesize this step.
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//
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// 3) IQ imbalance correction. This implements a simple, one-shot IQ imbalance
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// correction. It will modify the I and Q signals as follows:
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// _ _ _ _ _ _
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// | I' | | A/64+1 0 | | I |
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// | | = | | | |
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// | Q' | | B/64 1 | | Q |
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// ‾ ‾ ‾ ‾ ‾ ‾
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//
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// Here, A is the value written to the register at SR_MAG_CORRECTION, and
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// B is the value written to the register at SR_PHASE_CORRECTION.
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// Set BYPASS_IQ_COMP to 1 to not synthesize this step.
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//
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// 4) Heterodyne conversion. The converter is only enabled when the
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// "downconvert" bit in the SR_IQ_MAPPING register is asserted. In this
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// case, it enables a quarter-rate mixer. The direction of this mixer is
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// controlled by the SR_HET_PHASE_INCR register (a 0 in this register
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// rotates by pi/2 every clock cycle, a 1 in this register rotates by -pi/2).
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//
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// The mixer is followed by a non-decimating FIR filter.
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//
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// Set BYPASS_HETERODYNE to 1 to not synthesize this step.
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//
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//
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// UHD Developers Note: This module is typically controlled by rx_frontend_core_3000 in UHD,
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// and is also described in the calibration.dox manual page. When modifying this file, make
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// sure to also modify those files if necessary.
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//
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// Parameters:
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// SR_MAG_CORRECTION : Settings register address for the IQ correction "MAG" value
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// SR_PHASE_CORRECTION : Settings register address for the IQ correction "PHASE" value
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// SR_OFFSET_I : Settings register address for DC offset I correction
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// value (goes to rx_dcoffset)
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// SR_OFFSET_Q : Settings register address for DC offset Q correction
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// value (goes to rx_dcoffset)
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// SR_IQ_MAPPING : Settings register address for IQ mapping value
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// SR_HET_PHASE_INCR : Settings register address for the real mode phase
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// increment value
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// BYPASS_DC_OFFSET_CORR : Set to 1 to disable DC offset correction
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// BYPASS_IQ_COMP : Set to 1 to disable IQ offset correction
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// BYPASS_HETERODYNE : Set to 1 to disable heterodyne conversion
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// DEVICE : Unused.
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//
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module rx_frontend_gen3 #(
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parameter SR_MAG_CORRECTION = 0,
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parameter SR_PHASE_CORRECTION = 1,
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parameter SR_OFFSET_I = 2,
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parameter SR_OFFSET_Q = 3,
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parameter SR_IQ_MAPPING = 4,
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parameter SR_HET_PHASE_INCR = 5,
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parameter BYPASS_DC_OFFSET_CORR = 0,
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parameter BYPASS_IQ_COMP = 0,
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parameter BYPASS_HETERODYNE = 0,
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parameter DEVICE = "7SERIES"
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)(
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input clk, input reset, input sync_in,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input adc_stb, input [15:0] adc_i, input [15:0] adc_q,
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output rx_stb, output [15:0] rx_i, output [15:0] rx_q
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);
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wire realmode;
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wire swap_iq;
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wire invert_i;
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wire invert_q;
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wire downconvert;
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wire bypass_all;
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wire [1:0] iq_map_reserved;
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wire [17:0] mag_corr, phase_corr;
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wire phase_dir;
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wire phase_sync;
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reg [23:0] adc_i_mux, adc_q_mux;
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reg adc_mux_stb;
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wire [23:0] adc_i_ofs, adc_q_ofs, adc_i_comp, adc_q_comp;
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wire adc_ofs_stb, adc_comp_stb;
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reg [1:0] adc_ofs_stb_dly;
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wire [23:0] adc_i_dsp, adc_q_dsp;
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wire adc_dsp_stb;
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wire [15:0] rx_i_out, rx_q_out;
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/********************************************************
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** Settings Bus Registers
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********************************************************/
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setting_reg #(.my_addr(SR_MAG_CORRECTION),.width(18)) sr_mag_corr (
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.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(mag_corr),.changed());
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setting_reg #(.my_addr(SR_PHASE_CORRECTION),.width(18)) sr_phase_corr (
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.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_corr),.changed());
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setting_reg #(.my_addr(SR_IQ_MAPPING), .width(8)) sr_mux_sel (
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.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),
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.out({bypass_all,iq_map_reserved,downconvert,invert_i,invert_q,realmode,swap_iq}),
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.changed());
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// Setting reg: 1 bit to set phase direction: default to 0:
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// direction bit == 0: the phase is increased by pi/2 (counter clockwise)
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// direction bit == 1: the phase is increased by -pi/2 (clockwise)
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setting_reg #(.my_addr(SR_HET_PHASE_INCR), .width(1)) sr_phase_dir (
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.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_dir),.changed(phase_sync));
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/********************************************************
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** IQ Mapping (swapping, inversion, real-mode)
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********************************************************/
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// MUX so we can do realmode signals on either input
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always @(posedge clk) begin
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if (swap_iq) begin
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adc_i_mux[23:8] <= invert_q ? ~adc_q : adc_q;
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adc_q_mux[23:8] <= realmode ? 16'd0 : invert_i ? ~adc_i : adc_i;
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end else begin
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adc_i_mux[23:8] <= invert_i ? ~adc_i : adc_i;
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adc_q_mux[23:8] <= realmode ? 16'd0 : invert_q ? ~adc_q : adc_q;
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end
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adc_mux_stb <= adc_stb;
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adc_i_mux[7:0] <= 8'd0;
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adc_q_mux[7:0] <= 8'd0;
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end
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/********************************************************
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** DC offset Correction
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********************************************************/
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generate
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if (BYPASS_DC_OFFSET_CORR == 0) begin
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rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_I)) rx_dcoffset_i (
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.clk(clk),.rst(reset),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.in_stb(adc_mux_stb),.in(adc_i_mux),
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.out_stb(adc_ofs_stb),.out(adc_i_ofs));
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rx_dcoffset #(.WIDTH(24),.ADDR(SR_OFFSET_Q)) rx_dcoffset_q (
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.clk(clk),.rst(reset),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.in_stb(adc_mux_stb),.in(adc_q_mux),
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.out_stb(),.out(adc_q_ofs));
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end else begin
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assign adc_ofs_stb = adc_mux_stb;
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assign adc_i_ofs = adc_i_mux;
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assign adc_q_ofs = adc_q_mux;
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end
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endgenerate
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/********************************************************
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** IQ Imbalance Compensation
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********************************************************/
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generate
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if (BYPASS_IQ_COMP == 0) begin
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mult_add_clip #(
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.WIDTH_A(18),
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.BIN_PT_A(17),
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.WIDTH_B(18),
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.BIN_PT_B(17),
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.WIDTH_C(24),
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.BIN_PT_C(23),
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.WIDTH_O(24),
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.BIN_PT_O(23),
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.LATENCY(2)
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) mult_i (
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.clk(clk),
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.reset(reset),
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.CE(1'b1),
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.A(adc_i_ofs[23:6]),
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.B(mag_corr),
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.C(adc_i_ofs),
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.O(adc_i_comp)
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);
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mult_add_clip #(
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.WIDTH_A(18),
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.BIN_PT_A(17),
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.WIDTH_B(18),
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.BIN_PT_B(17),
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.WIDTH_C(24),
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.BIN_PT_C(23),
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.WIDTH_O(24),
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.BIN_PT_O(23),
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.LATENCY(2)
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) mult_q (
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.clk(clk),
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.reset(reset),
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.CE(1'b1),
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.A(adc_i_ofs[23:6]),
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.B(phase_corr),
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.C(adc_q_ofs),
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.O(adc_q_comp)
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);
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// Delay to match path latencies
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always @(posedge clk) begin
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if (reset) begin
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adc_ofs_stb_dly <= 2'b0;
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end else begin
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adc_ofs_stb_dly <= {adc_ofs_stb_dly[0], adc_ofs_stb};
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end
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end
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assign adc_comp_stb = adc_ofs_stb_dly[1];
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end else begin
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assign adc_comp_stb = adc_ofs_stb;
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assign adc_i_comp = adc_i_ofs;
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assign adc_q_comp = adc_q_ofs;
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end
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endgenerate
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/********************************************************
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** Realmode DSP:
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* - Heterodyne frequency translation
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* - Realmode decimation (by 2)
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********************************************************/
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generate
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if (BYPASS_HETERODYNE == 0) begin
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wire [23:0] adc_i_dsp_cout, adc_q_dsp_cout;
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wire [23:0] adc_i_filt, adc_q_filt;
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wire adc_dsp_cout_stb;
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wire adc_filt_stb;
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// 90 degree mixer
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quarter_rate_downconverter #(.WIDTH(24)) qr_dc_i(
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.clk(clk), .reset(reset || sync_in), .phase_sync(phase_sync),
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.i_tdata({adc_i_comp, adc_q_comp}), .i_tlast(1'b1), .i_tvalid(adc_comp_stb), .i_tready(),
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.o_tdata({adc_i_dsp_cout, adc_q_dsp_cout}), .o_tlast(), .o_tvalid(adc_dsp_cout_stb), .o_tready(1'b1),
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.dirctn(phase_dir));
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// Double FIR block
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localparam HB_COEFS = {-18'd62, 18'd0, 18'd194, 18'd0, -18'd440, 18'd0, 18'd855, 18'd0, -18'd1505, 18'd0, 18'd2478, 18'd0,
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-18'd3900, 18'd0, 18'd5990, 18'd0, -18'd9187, 18'd0, 18'd14632, 18'd0, -18'd26536, 18'd0, 18'd83009, 18'd131071, 18'd83009,
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18'd0, -18'd26536, 18'd0, 18'd14632, 18'd0, -18'd9187, 18'd0, 18'd5990, 18'd0, -18'd3900, 18'd0, 18'd2478, 18'd0, -18'd1505,
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18'd0, 18'd855, 18'd0, -18'd440, 18'd0, 18'd194, 18'd0, -18'd62};
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// FIR filter for real part
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axi_fir_filter #(.IN_WIDTH(24), .COEFF_WIDTH(18), .OUT_WIDTH(24), .NUM_COEFFS(47), .COEFFS_VEC(HB_COEFS),
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.RELOADABLE_COEFFS(0), .BLANK_OUTPUT(0), .SYMMETRIC_COEFFS(1), .SKIP_ZERO_COEFFS(1), .USE_EMBEDDED_REGS_COEFFS(0)
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) hbfir0(
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.clk(clk),
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.reset(reset),
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.clear(reset),
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.s_axis_data_tdata(adc_i_dsp_cout),
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.s_axis_data_tlast(1'b1),
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.s_axis_data_tvalid(adc_dsp_cout_stb),
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.s_axis_data_tready(),
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.m_axis_data_tdata(adc_i_filt),
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.m_axis_data_tlast(),
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.m_axis_data_tvalid(adc_filt_stb),
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.m_axis_data_tready(1'b1),
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.s_axis_reload_tdata(18'd0),
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.s_axis_reload_tvalid(1'b0),
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.s_axis_reload_tlast(1'b0),
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.s_axis_reload_tready()
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);
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// FIR filter for imag. part
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axi_fir_filter #(.IN_WIDTH(24), .COEFF_WIDTH(18), .OUT_WIDTH(24), .NUM_COEFFS(47), .COEFFS_VEC(HB_COEFS),
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.RELOADABLE_COEFFS(0), .BLANK_OUTPUT(0), .SYMMETRIC_COEFFS(1), .SKIP_ZERO_COEFFS(1), .USE_EMBEDDED_REGS_COEFFS(0)
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) hbfir1(
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.clk(clk),
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.reset(reset),
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.clear(reset),
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.s_axis_data_tdata(adc_q_dsp_cout),
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.s_axis_data_tlast(1'b1),
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.s_axis_data_tvalid(adc_dsp_cout_stb),
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.s_axis_data_tready(),
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.m_axis_data_tdata(adc_q_filt),
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.m_axis_data_tlast(),
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.m_axis_data_tvalid(),
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.m_axis_data_tready(1'b1),
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.s_axis_reload_tdata(18'd0),
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.s_axis_reload_tvalid(1'b0),
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.s_axis_reload_tlast(1'b0),
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.s_axis_reload_tready()
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);
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assign adc_dsp_stb = downconvert ? adc_filt_stb : adc_comp_stb;
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assign adc_i_dsp = downconvert ? adc_i_filt : adc_i_comp;
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assign adc_q_dsp = downconvert ? adc_q_filt : adc_q_comp;
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end else begin
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assign adc_dsp_stb = adc_comp_stb;
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assign adc_i_dsp = adc_i_comp;
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assign adc_q_dsp = adc_q_comp;
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end
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endgenerate
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// Round to short complex (sc16)
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round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_i (
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.clk(clk),.reset(reset), .in(adc_i_dsp),.strobe_in(adc_dsp_stb), .out(rx_i_out), .strobe_out(rx_stb));
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round_sd #(.WIDTH_IN(24),.WIDTH_OUT(16)) round_q (
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.clk(clk),.reset(reset), .in(adc_q_dsp),.strobe_in(adc_dsp_stb), .out(rx_q_out), .strobe_out());
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assign rx_i = bypass_all ? adc_i : rx_i_out;
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assign rx_q = bypass_all ? adc_q : rx_q_out;
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endmodule
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