Wade Fife 287659ddeb fpga: Fix first arg in calls to $fatal() ...

This fixes warnings regarding the first argument to $fatal(), which is
supposed to be a number indicating what diagnostics to display. 1
corresponds to "Prints simulation time and location".


Original-commit: 58763bdfdaa276155ec6b79a3e5420de17172c7a

2022-06-28 10:34:18 -05:00

..

test/ChdrIfaceBfm

sim: Add ChdrIfaceBfm test

2020-03-09 13:43:05 -05:00

Makefile.srcs

fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh

2022-01-25 14:09:15 -07:00

PkgAxiLiteBfm.sv

fpga: sim: Fix AxiLiteBfm

2020-07-31 13:10:00 -05:00

PkgAxisCtrlBfm.sv

fpga: lib: Add synthesizable AXI4-Stream SV components

2020-06-25 14:44:04 -05:00

PkgAxiStreamBfm.sv

fpga: Fix first arg in calls to $fatal()

2022-06-28 10:34:18 -05:00

PkgChdrBfm.sv

fpga: sim: Fix stream command and status models

2020-08-31 08:16:43 -05:00

PkgChdrData.sv

fpga: sim: Add packet_info_equal function

2020-05-28 15:04:05 -05:00

PkgChdrIfaceBfm.sv

fpga: sim: Add packet_info_equal function

2020-05-28 15:04:05 -05:00

PkgChdrUtils.sv

sim: Parameterize chdr_word_t data type

2020-03-09 13:43:05 -05:00

PkgCtrlIfaceBfm.sv

sim: Split PkgRfnocBlockCtrlBfm into separate packages

2020-03-09 13:43:05 -05:00

PkgEthernet.sv

fpga: sim: Check for empty packet in clear_unused_bytes

2021-06-17 08:16:59 -05:00

PkgRfnocBlockCtrlBfm.sv

fpga: sim: Add packet_info_equal function

2020-05-28 15:04:05 -05:00

PkgRfnocItemUtils.sv

fpga: rfnoc: Add support for 512-bit CHDR widths

2020-06-18 09:09:34 -05:00

PkgTestExec.sv

fpga: rfnoc: Add support for 512-bit CHDR widths

2020-06-18 09:09:34 -05:00

sim_clock_gen.sv

fpga: lib: Add PHASE parameter to sim_clk_gen

2021-06-03 11:26:54 -05:00

test_exec.svh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00