402 lines
15 KiB
Verilog
402 lines
15 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ipv4_chdr64_adapter
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// Description: A generic transport adapter module that can be used in
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// a veriety of transports. It does the following:
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// - Exposes a configuration port for mgmt packets to configure the node
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// - Implements a return-address map for packets with metadata other than
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// the CHDR. Additional metadata can be passed as a tuser to this module
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// which will store it in a map indexed by the SrcEPID in a management
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// packet. For all returning packets, the metadata will be looked up in
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// the map and attached as the outgoing tuser.
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// - Implements a loopback path for node-info discovery
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - MTU: Log2 of the MTU of the packet in 64-bit words
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// - CPU_FIFO_SIZE: Log2 of the FIFO depth (in 64-bit words) for the CPU egress path
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// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
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// - NODE_INST: The node type to return for a node-info discovery
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// - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
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//
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// Signals:
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// - device_id : The ID of the device that has instantiated this module
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// - s_mac_*: The input Ethernet stream from the MAC (plus tuser for trailing bytes + err)
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// - m_mac_*: The output Ethernet stream to the MAC (plus tuser for trailing bytes + err)
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// - s_chdr_*: The input CHDR stream from the rfnoc infrastructure
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// - m_chdr_*: The output CHDR stream to the rfnoc infrastructure
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// - s_cpu_*: The input Ethernet stream from the CPU (plus tuser for trailing bytes + err)
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// - m_cpu_*: The output Ethernet stream to the CPU (plus tuser for trailing bytes + err)
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// - my_eth_addr: The Ethernet (MAC) address of this endpoint
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// - my_ipv4_addr: The IPv4 address of this endpoint
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// - my_udp_chdr_port: The UDP port allocated for CHDR traffic on this endpoint
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//
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`default_nettype none
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module eth_ipv4_chdr64_adapter #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter MTU = 10,
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parameter CPU_FIFO_SIZE = MTU,
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parameter RT_TBL_SIZE = 6,
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parameter NODE_INST = 0,
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parameter [0:0] DROP_UNKNOWN_MAC = 1,
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parameter [0:0] IS_CPU_ARM = 0
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)(
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// Clocking and reset interface
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input wire clk,
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input wire rst,
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// Device info
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input wire [15:0] device_id,
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// AXI-Stream interface to/from MAC
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input wire [63:0] s_mac_tdata,
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input wire [3:0] s_mac_tuser,
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input wire s_mac_tlast,
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input wire s_mac_tvalid,
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output wire s_mac_tready,
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output wire [63:0] m_mac_tdata,
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output wire [3:0] m_mac_tuser,
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output wire m_mac_tlast,
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output wire m_mac_tvalid,
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input wire m_mac_tready,
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// AXI-Stream interface to/from CHDR infrastructure
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input wire [63:0] s_chdr_tdata,
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input wire s_chdr_tlast,
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input wire s_chdr_tvalid,
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output wire s_chdr_tready,
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output wire [63:0] m_chdr_tdata,
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output wire m_chdr_tlast,
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output wire m_chdr_tvalid,
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input wire m_chdr_tready,
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// AXI-Stream interface to/from CPU
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input wire [63:0] s_cpu_tdata,
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input wire [3:0] s_cpu_tuser,
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input wire s_cpu_tlast,
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input wire s_cpu_tvalid,
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output wire s_cpu_tready,
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output wire [63:0] m_cpu_tdata,
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output wire [3:0] m_cpu_tuser,
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output wire m_cpu_tlast,
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output wire m_cpu_tvalid,
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input wire m_cpu_tready,
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// Device addresses
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input wire [47:0] my_eth_addr,
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input wire [31:0] my_ipv4_addr,
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input wire [15:0] my_udp_chdr_port
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);
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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`include "rfnoc_xport_types.vh"
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//-----------------------------------------------------------------------
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// Byte-swapping function
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// Ethernet fields we wrote out left-to-right, but AXI-Stream time-orders
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// its data right-to-left.
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//-----------------------------------------------------------------------
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function [63:0] bswap64(
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input [63:0] din
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);
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begin
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bswap64 = {din[0 +: 8], din[8 +: 8], din[16 +: 8], din[24 +: 8],
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din[32+: 8], din[40+: 8], din[48 +: 8], din[56 +: 8]};
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end
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endfunction
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//---------------------------------------
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// E2X and E2C DEMUX
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//---------------------------------------
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wire [63:0] e2x_chdr_tdata;
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wire [95:0] e2x_chdr_tuser;
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wire e2x_chdr_tlast, e2x_chdr_tvalid, e2x_chdr_tready;
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wire [63:0] e2c_chdr_tdata;
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wire [3:0] e2c_chdr_tuser;
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wire e2c_chdr_tlast, e2c_chdr_tvalid, e2c_chdr_tready;
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// Ethernet sink. Inspects packet and dispatches
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// to the correct port.
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eth_ipv4_chdr64_dispatch #(
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.DROP_UNKNOWN_MAC(DROP_UNKNOWN_MAC)
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) eth_dispatch_i (
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.clk (clk),
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.rst (rst),
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.s_mac_tdata (s_mac_tdata),
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.s_mac_tuser (s_mac_tuser),
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.s_mac_tlast (s_mac_tlast),
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.s_mac_tvalid (s_mac_tvalid),
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.s_mac_tready (s_mac_tready),
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.m_chdr_tdata (e2x_chdr_tdata),
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.m_chdr_tuser (e2x_chdr_tuser),
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.m_chdr_tlast (e2x_chdr_tlast),
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.m_chdr_tvalid (e2x_chdr_tvalid),
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.m_chdr_tready (e2x_chdr_tready),
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.m_cpu_tdata (e2c_chdr_tdata),
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.m_cpu_tuser (e2c_chdr_tuser),
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.m_cpu_tlast (e2c_chdr_tlast),
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.m_cpu_tvalid (e2c_chdr_tvalid),
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.m_cpu_tready (e2c_chdr_tready),
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.my_eth_addr (my_eth_addr),
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.my_ipv4_addr (my_ipv4_addr),
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.my_udp_chdr_port (my_udp_chdr_port)
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);
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//---------------------------------------
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// CHDR Transport Adapter
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//---------------------------------------
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wire [63:0] x2e_chdr_tdata;
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wire [95:0] x2e_chdr_tuser;
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wire x2e_chdr_tlast, x2e_chdr_tvalid, x2e_chdr_tready;
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wire [63:0] e2x_fifo_tdata;
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wire e2x_fifo_tlast, e2x_fifo_tvalid, e2x_fifo_tready;
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wire [63:0] e2c_fifo_tdata;
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wire [3:0] e2c_fifo_tuser;
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wire e2c_fifo_tlast, e2c_fifo_tvalid, e2c_fifo_tready;
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chdr_xport_adapter_generic #(
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.PROTOVER (PROTOVER),
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.CHDR_W (64),
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.USER_W (96),
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.TBL_SIZE (RT_TBL_SIZE),
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.NODE_SUBTYPE (NODE_SUBTYPE_XPORT_IPV4_CHDR64),
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.NODE_INST (NODE_INST),
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.ALLOW_DISC (1)
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) xport_adapter_gen_i (
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.clk (clk),
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.rst (rst),
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.device_id (device_id),
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.s_axis_xport_tdata (e2x_chdr_tdata),
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.s_axis_xport_tuser (e2x_chdr_tuser),
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.s_axis_xport_tlast (e2x_chdr_tlast),
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.s_axis_xport_tvalid (e2x_chdr_tvalid),
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.s_axis_xport_tready (e2x_chdr_tready),
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.m_axis_xport_tdata (x2e_chdr_tdata),
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.m_axis_xport_tuser (x2e_chdr_tuser),
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.m_axis_xport_tlast (x2e_chdr_tlast),
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.m_axis_xport_tvalid (x2e_chdr_tvalid),
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.m_axis_xport_tready (x2e_chdr_tready),
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.s_axis_rfnoc_tdata (s_chdr_tdata),
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.s_axis_rfnoc_tlast (s_chdr_tlast),
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.s_axis_rfnoc_tvalid (s_chdr_tvalid),
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.s_axis_rfnoc_tready (s_chdr_tready),
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.m_axis_rfnoc_tdata (e2x_fifo_tdata),
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.m_axis_rfnoc_tlast (e2x_fifo_tlast),
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.m_axis_rfnoc_tvalid (e2x_fifo_tvalid),
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.m_axis_rfnoc_tready (e2x_fifo_tready),
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.ctrlport_req_wr (/* unused */),
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.ctrlport_req_rd (/* unused */),
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.ctrlport_req_addr (/* unused */),
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.ctrlport_req_data (/* unused */),
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.ctrlport_resp_ack (/* unused */),
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.ctrlport_resp_data (/* unused */)
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);
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generate
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if (IS_CPU_ARM == 1'b1) begin
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//---------------------------------------
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// Ethernet framer for ARM
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//---------------------------------------
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// Strip the 6 octet ethernet padding we used internally
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// before sending to ARM.
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// Put SOF into bit[3] of tuser.
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axi64_to_xge64 arm_framer (
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.clk(clk),
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.reset(rst),
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.clear(1'b0),
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.s_axis_tdata(e2c_chdr_tdata),
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.s_axis_tuser(e2c_chdr_tuser),
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.s_axis_tlast(e2c_chdr_tlast),
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.s_axis_tvalid(e2c_chdr_tvalid),
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.s_axis_tready(e2c_chdr_tready),
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.m_axis_tdata(e2c_fifo_tdata),
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.m_axis_tuser(e2c_fifo_tuser),
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.m_axis_tlast(e2c_fifo_tlast),
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.m_axis_tvalid(e2c_fifo_tvalid),
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.m_axis_tready(e2c_fifo_tready)
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);
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end else begin
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assign e2c_fifo_tdata = e2c_chdr_tdata;
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assign e2c_fifo_tuser = e2c_chdr_tuser;
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assign e2c_fifo_tlast = e2c_chdr_tlast;
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assign e2c_fifo_tvalid = e2c_chdr_tvalid;
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assign e2c_chdr_tready = e2c_fifo_tready;
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end
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endgenerate
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//---------------------------------------
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// E2X and E2C Output Buffering
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//---------------------------------------
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// The CPU can be slow to respond (relative to packet wirespeed) so
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// extra buffer for packets destined there so it doesn't back up.
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axi_fifo #(
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.WIDTH(64+4+1),.SIZE(CPU_FIFO_SIZE)
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) cpu_fifo_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata({e2c_fifo_tlast, e2c_fifo_tuser, e2c_fifo_tdata}),
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.i_tvalid(e2c_fifo_tvalid), .i_tready(e2c_fifo_tready),
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.o_tdata({m_cpu_tlast, m_cpu_tuser, m_cpu_tdata}),
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.o_tvalid(m_cpu_tvalid), .o_tready(m_cpu_tready),
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.occupied(), .space()
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);
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// The transport should hook up to a crossbar downstream, which
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// may backpressure this module because it is in the middle of
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// transferring a packet. To ensure that upstream logic is not
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// blocked, we instantiate one packet worth of buffering here.
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axi_fifo #(
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.WIDTH(64+1),.SIZE(MTU)
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) chdr_fifo_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata({e2x_fifo_tlast, e2x_fifo_tdata}),
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.i_tvalid(e2x_fifo_tvalid), .i_tready(e2x_fifo_tready),
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.o_tdata({m_chdr_tlast, m_chdr_tdata}),
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.o_tvalid(m_chdr_tvalid), .o_tready(m_chdr_tready),
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.occupied(), .space()
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);
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//---------------------------------------
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// Ethernet Framer for X2E
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//---------------------------------------
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wire [63:0] x2e_framed_tdata;
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wire [3:0] x2e_framed_tuser;
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wire x2e_framed_tlast, x2e_framed_tvalid, x2e_framed_tready;
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localparam [2:0] ST_IDLE = 3'd0;
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localparam [2:0] ST_ETH_L0 = 3'd1;
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localparam [2:0] ST_ETH_L1 = 3'd2;
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localparam [2:0] ST_ETH_L2_IPV4_L0 = 3'd3;
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localparam [2:0] ST_IPV4_L1 = 3'd4;
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localparam [2:0] ST_IPV4_L2 = 3'd5;
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localparam [2:0] ST_IPV4_UDP_HDR = 3'd6;
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localparam [2:0] ST_CHDR_PAYLOAD = 3'd7;
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reg [2:0] frame_state = ST_IDLE;
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reg [15:0] chdr_len = 16'd0;
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reg [63:0] frame_tdata;
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always @(posedge clk) begin
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if(rst) begin
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frame_state <= ST_IDLE;
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chdr_len <= 16'd0;
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end else begin
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case(frame_state)
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ST_IDLE: begin
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if (x2e_chdr_tvalid) begin
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frame_state <= ST_ETH_L0;
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chdr_len <= chdr_get_length(x2e_chdr_tdata);
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end
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end
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ST_CHDR_PAYLOAD: begin
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if (x2e_chdr_tvalid & x2e_framed_tready)
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if (x2e_chdr_tlast)
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frame_state <= ST_IDLE;
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end
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default: begin
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if(x2e_framed_tready)
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frame_state <= frame_state + 3'd1;
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end
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endcase
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end
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end
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assign x2e_chdr_tready = (frame_state == ST_CHDR_PAYLOAD) ? x2e_framed_tready : 1'b0;
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assign x2e_framed_tvalid = (frame_state == ST_CHDR_PAYLOAD) ? x2e_chdr_tvalid : (frame_state == ST_IDLE) ? 1'b0 : 1'b1;
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assign x2e_framed_tlast = (frame_state == ST_CHDR_PAYLOAD) ? x2e_chdr_tlast : 1'b0;
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assign x2e_framed_tuser = ((frame_state == ST_CHDR_PAYLOAD) & x2e_chdr_tlast) ? {1'b0, chdr_len[2:0]} : 4'b0000;
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assign x2e_framed_tdata = frame_tdata;
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wire [47:0] pad = 48'h0;
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wire [47:0] mac_dst = x2e_chdr_tuser[47:0]; // Extract from router lookup results
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wire [15:0] eth_type = 16'h0800; // IPv4
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wire [15:0] misc_ip = { 4'd4 /* IPv4 */, 4'd5 /* IP HDR Len */, 8'h00 /* DSCP and ECN */};
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wire [15:0] ip_len = (16'd28 + chdr_len); // 20 for IP, 8 for UDP
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wire [15:0] ident = 16'h0;
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wire [15:0] flag_frag = { 3'b010 /* don't fragment */, 13'h0 };
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wire [15:0] ttl_prot = { 8'h10 /* TTL */, 8'h11 /* UDP */ };
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wire [15:0] iphdr_checksum;
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wire [31:0] ip_dst = x2e_chdr_tuser[79:48]; // Extract from router lookup results
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wire [15:0] udp_dst = x2e_chdr_tuser[95:80]; // Extract from router lookup results
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wire [15:0] udp_len = (16'd8 + chdr_len);
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wire [15:0] udp_checksum = 16'h0;
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ip_hdr_checksum ip_hdr_checksum (
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.clk(clk), .in({misc_ip, ip_len, ident, flag_frag, ttl_prot, 16'd0, my_ipv4_addr, ip_dst}),
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.out(iphdr_checksum)
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);
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always @(*) begin
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case(frame_state)
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ST_ETH_L0 : frame_tdata <= bswap64({pad[47:0], mac_dst[47:32]});
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ST_ETH_L1 : frame_tdata <= bswap64({mac_dst[31:0], my_eth_addr[47:16]});
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ST_ETH_L2_IPV4_L0 : frame_tdata <= bswap64({my_eth_addr[15:0], eth_type[15:0], misc_ip[15:0], ip_len[15:0]});
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ST_IPV4_L1 : frame_tdata <= bswap64({ident[15:0], flag_frag[15:0], ttl_prot[15:0], iphdr_checksum[15:0]});
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ST_IPV4_L2 : frame_tdata <= bswap64({my_ipv4_addr[31:0], ip_dst[31:0]});
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ST_IPV4_UDP_HDR : frame_tdata <= bswap64({my_udp_chdr_port[15:0], udp_dst[15:0], udp_len[15:0], udp_checksum[15:0]});
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default : frame_tdata <= x2e_chdr_tdata;
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endcase
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end
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wire [63:0] c2e_tdata;
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wire [3:0] c2e_tuser;
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wire c2e_tlast;
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wire c2e_tvalid;
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wire c2e_tready;
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generate
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if (IS_CPU_ARM == 1'b1) begin
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//---------------------------------------
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// Ethernet deframer for ARM
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//---------------------------------------
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// Add pad of 6 empty bytes to the ethernet packet going from the CPU to the
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// SFP. This padding added before MAC addresses aligns the source and
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// destination IP addresses, UDP headers etc.
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// Note that the xge_mac_wrapper strips this padding to recreate the ethernet
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// packet
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arm_deframer inst_arm_deframer
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(
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.clk(clk),
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.reset(rst),
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.clear(1'b0),
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.s_axis_tdata(s_cpu_tdata),
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.s_axis_tuser(s_cpu_tuser),
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.s_axis_tlast(s_cpu_tlast),
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.s_axis_tvalid(s_cpu_tvalid),
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.s_axis_tready(s_cpu_tready),
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.m_axis_tdata(c2e_tdata),
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.m_axis_tuser(c2e_tuser),
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.m_axis_tlast(c2e_tlast),
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.m_axis_tvalid(c2e_tvalid),
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.m_axis_tready(c2e_tready)
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);
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end else begin
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assign c2e_tdata = s_cpu_tdata;
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assign c2e_tuser = s_cpu_tuser;
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assign c2e_tlast = s_cpu_tlast;
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assign c2e_tvalid = s_cpu_tvalid;
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assign s_cpu_tready = c2e_tready;
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end
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endgenerate
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//---------------------------------------
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// X2E and C2E MUX
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//---------------------------------------
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axi_mux #(
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.SIZE(2), .PRIO(0), .WIDTH(64+4), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
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) eth_mux_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata({c2e_tuser, c2e_tdata, x2e_framed_tuser, x2e_framed_tdata}), .i_tlast({c2e_tlast, x2e_framed_tlast}),
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.i_tvalid({c2e_tvalid, x2e_framed_tvalid}), .i_tready({c2e_tready, x2e_framed_tready}),
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.o_tdata({m_mac_tuser, m_mac_tdata}), .o_tlast(m_mac_tlast),
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.o_tvalid(m_mac_tvalid), .o_tready(m_mac_tready)
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);
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endmodule // eth_ipv4_chdr64_adapter
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`default_nettype wire
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