miegl/b210-k7-fpga
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b210-k7-fpga/lib/rfnoc/crossbar
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Wade Fife c33b3779f9 fpga: Change default MTU to 10 
Original-commit: 7b7fa68880ca423ea3a47fc3dc97ba533921c9a5
2020-05-11 09:06:03 -05:00
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crossbar_tb
fpga: Fix errors found by linting with vsim
2020-03-23 08:23:51 -05:00
synth
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_ctrl_crossbar_2d_mesh.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_ctrl_crossbar_nxn.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_ingress_vc_buff.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_port_terminator.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_switch.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_crossbar_nxn.v
fpga: Change default MTU to 10
2020-05-11 09:06:03 -05:00
chdr_xb_ingress_buff.v
fpga: Change default MTU to 10
2020-05-11 09:06:03 -05:00
chdr_xb_routing_table.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gen_node_to_coord_mapping.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mesh_2d_dor_router_multi_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mesh_2d_dor_router_single_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mesh_node_mapping.vh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
README.pdf
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
torus_2d_dor_router_multi_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
torus_2d_dor_router_single_sw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00