This adds a simulation make target that allows you to run ModelSim
natively rather than through Vivado.
Adds or modifies the following simulation make targets:
make vlint - Brake up compilation to Verilog/SystemVerilog/VHDL
make modelsim - Depends on make vlint and invokes modelsim
Adds the following variables:
MODELSIM_ARGS - Added to invocation of ModelSim
SVLOG_ARGS - Added to SystemVerilog invocation of vlog
VLOG_ARGS - Added to Verilog invocation of vlog
VHDL_ARGS - Added to VHDL invocation of vcom
Original-commit: b296b26053d4437b8ae97e3df415a3d041b7b51e
Andrew Moch
09751b661e