61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
324 lines
12 KiB
Verilog
324 lines
12 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: db_gpio_interface
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//
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// Description:
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// Interface for GPIO interface towards daughterboards.
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//
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// A ControlPort interface is serialized into bytes along with a valid signal.
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// The ControlPort supports write requests only. Byte enables are not supported.
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// There is support for timed commands.
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// Furthermore there are 4 state wires towards the DB. Ensure an appropriate
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// hold time on the states as the transmission happens in pll_ref_clk, which is
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// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get
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// transferred to the DB.
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//
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// The 20 available GPIO lines are assigned with
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// - 5x empty
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// - bytestream direction
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// - bytestream valid
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// - bytestream data (8 bits)
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// - 1x empty
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// - db_state (4 bits)
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//
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`default_nettype none
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module db_gpio_interface (
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// Clocks and reset
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input wire radio_clk,
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input wire pll_ref_clk,
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// DB state lines (domain: radio_clk)
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input wire [ 3:0] db_state,
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// time interfaces (domain: radio_clk)
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input wire [63:0] radio_time,
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input wire radio_time_stb,
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input wire [ 3:0] time_ignore_bits,
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// Request (domain: radio_clk)
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input wire ctrlport_rst,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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// Response (domain: radio_clk)
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// GPIO interface (domain: pll_ref_clk)
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input wire [19:0] gpio_in,
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output wire [19:0] gpio_out,
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output wire [19:0] gpio_out_en,
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// Version (Constant)
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output wire [95:0] version_info
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);
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`include "../regmap/versioning_regs_regmap_utils.vh"
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`include "../regmap/versioning_utils.vh"
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//----------------------------------------------------------------------------
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// Timed command processing
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//----------------------------------------------------------------------------
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wire [19:0] ctrlport_timed_req_addr;
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wire [31:0] ctrlport_timed_req_data;
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wire ctrlport_timed_req_rd;
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wire ctrlport_timed_req_wr;
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wire ctrlport_timed_resp_ack;
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reg [31:0] ctrlport_timed_resp_data = 0;
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reg [ 1:0] ctrlport_timed_resp_status = 0;
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ctrlport_timer #(
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.EXEC_LATE_CMDS(1)
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) ctrlport_timer_i (
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.clk (radio_clk),
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.rst (ctrlport_rst),
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.time_now (radio_time),
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.time_now_stb (radio_time_stb),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
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.s_ctrlport_req_time (s_ctrlport_req_time),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.m_ctrlport_req_wr (ctrlport_timed_req_wr),
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.m_ctrlport_req_rd (ctrlport_timed_req_rd),
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.m_ctrlport_req_addr (ctrlport_timed_req_addr),
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.m_ctrlport_req_data (ctrlport_timed_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_resp_ack (ctrlport_timed_resp_ack),
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.m_ctrlport_resp_status (ctrlport_timed_resp_status),
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.m_ctrlport_resp_data (ctrlport_timed_resp_data)
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);
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//----------------------------------------------------------------------------
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// Clock domain crossing (radio_clk -> pll_ref_clk)
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//----------------------------------------------------------------------------
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// Radio_clk is derived from pll_ref_clk by an integer multiplier and
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// originate from the same PLL.
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// Therefore the clock crossing can be achieved by using simple registers.
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// Static timing analysis will be able to meet setup and hold requirements on
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// them.
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// holding read and write flags for multiple radio_clk cycles
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reg ctrlport_timed_req_wr_hold = 1'b0;
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reg ctrlport_timed_req_rd_hold = 1'b0;
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reg [19:0] ctrlport_req_addr_prc = 20'b0;
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reg [31:0] ctrlport_req_data_prc = 32'b0;
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reg ctrlport_req_rd_prc = 1'b0;
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reg ctrlport_req_wr_prc = 1'b0;
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wire ctrlport_resp_ack_prc;
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wire [31:0] ctrlport_resp_data_prc;
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wire [ 1:0] ctrlport_resp_status_prc;
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reg ctrlport_req_rd_fall = 1'b0;
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reg ctrlport_req_wr_fall = 1'b0;
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reg [31:0] ctrlport_resp_data_fall = 32'b0;
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reg [ 1:0] ctrlport_resp_status_fall = 2'b0;
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reg ctrlport_resp_ack_fall = 1'b0;
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// Retime signals to falling edge of radio_clk.
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// Because radio_clk is more heavily loaded than pll_ref_clk, it arrives at
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// the FF's later, which leads to hold time violations when moving signals
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// from pll_ref_clk to radio_clk. By sampling on the falling edge of
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// radio_clk, we provide (nominally) half a radio_clk period of hold, while
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// reducing setup time by half. The late arrival of radio_clk adds back some
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// of the lost setup margin.
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always @(negedge radio_clk) begin
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ctrlport_req_rd_fall <= ctrlport_req_rd_prc;
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ctrlport_req_wr_fall <= ctrlport_req_wr_prc;
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ctrlport_resp_ack_fall <= ctrlport_resp_ack_prc;
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ctrlport_resp_status_fall <= ctrlport_resp_status_prc;
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ctrlport_resp_data_fall <= ctrlport_resp_data_prc;
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end
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always @(posedge radio_clk) begin
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if (ctrlport_req_wr_fall) begin
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ctrlport_timed_req_wr_hold <= 1'b0;
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end else if (ctrlport_timed_req_wr) begin
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ctrlport_timed_req_wr_hold <= 1'b1;
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end
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if (ctrlport_req_rd_fall) begin
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ctrlport_timed_req_rd_hold <= 1'b0;
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end else if (ctrlport_timed_req_rd) begin
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ctrlport_timed_req_rd_hold <= 1'b1;
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end
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// capture request address and data
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if (ctrlport_timed_req_wr || ctrlport_timed_req_rd) begin
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ctrlport_req_addr_prc <= ctrlport_timed_req_addr;
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ctrlport_req_data_prc <= ctrlport_timed_req_data;
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end
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end
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// capture extended flags in pll_ref_clk domain
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always @(posedge pll_ref_clk) begin
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ctrlport_req_wr_prc <= ctrlport_timed_req_wr_hold;
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ctrlport_req_rd_prc <= ctrlport_timed_req_rd_hold;
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end
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// search for rising edge in response
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reg [1:0] ctrlport_timed_ack_reg = 2'b0;
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always @(posedge radio_clk) begin
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ctrlport_timed_ack_reg = {ctrlport_timed_ack_reg[0], ctrlport_resp_ack_fall};
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end
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assign ctrlport_timed_resp_ack = ctrlport_timed_ack_reg[0] & ~ctrlport_timed_ack_reg[1];
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// capture response data
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always @(posedge radio_clk) begin
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if (ctrlport_resp_ack_fall) begin
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ctrlport_timed_resp_status <= ctrlport_resp_status_fall;
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ctrlport_timed_resp_data <= ctrlport_resp_data_fall;
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end
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end
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// transfer state lines
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reg [3:0] db_state_prc = 4'b0;
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reg [3:0] db_state_prc_fe = 4'b0;
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always @(posedge pll_ref_clk) begin
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db_state_prc <= db_state;
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end
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always @(negedge pll_ref_clk) begin
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db_state_prc_fe <= db_state_prc;
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end
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// transfer reset
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reg ctrlport_rst_hold = 1'b0;
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reg ctrlport_rst_prc = 1'b0;
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reg ctrlport_rst_fall = 1'b0;
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always @(posedge radio_clk) begin
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if (ctrlport_rst) begin
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ctrlport_rst_hold <= 1'b1;
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end else if (ctrlport_rst_fall) begin
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ctrlport_rst_hold <= 1'b0;
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end
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end
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always @(posedge pll_ref_clk) begin
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ctrlport_rst_prc <= ctrlport_rst_hold;
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end
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always @(negedge radio_clk) begin
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ctrlport_rst_fall <= ctrlport_rst_prc;
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end
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//----------------------------------------------------------------------------
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// Ctrlport serializer
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//----------------------------------------------------------------------------
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wire [7:0] bytestream_data_in;
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wire [7:0] bytestream_data_out;
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wire bytestream_direction;
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wire bytestream_output_enable;
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wire bytestream_valid_in;
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wire bytestream_valid_out;
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ctrlport_byte_serializer serializer_i (
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.ctrlport_clk (pll_ref_clk),
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.ctrlport_rst (ctrlport_rst_prc),
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.s_ctrlport_req_wr (ctrlport_req_wr_prc),
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.s_ctrlport_req_rd (ctrlport_req_rd_prc),
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.s_ctrlport_req_addr (ctrlport_req_addr_prc),
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.s_ctrlport_req_data (ctrlport_req_data_prc),
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.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
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.s_ctrlport_resp_status (ctrlport_resp_status_prc),
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.s_ctrlport_resp_data (ctrlport_resp_data_prc),
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.bytestream_data_in (bytestream_data_in),
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.bytestream_valid_in (bytestream_valid_in),
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.bytestream_data_out (bytestream_data_out),
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.bytestream_valid_out (bytestream_valid_out),
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.bytestream_direction (bytestream_direction),
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.bytestream_output_enable (bytestream_output_enable)
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);
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// IOB registers to drive data on the falling edge
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reg [7:0] bytestream_data_out_fe;
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reg bytestream_direction_fe;
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reg bytestream_output_enable_fe;
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reg bytestream_valid_out_fe;
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// Signals are shifted into a falling edge domain to help meet
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// hold requirements at CPLD
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always @(negedge pll_ref_clk) begin
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if (ctrlport_rst_prc) begin
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bytestream_data_out_fe <= 8'b0;
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bytestream_valid_out_fe <= 1'b0;
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bytestream_direction_fe <= 1'b0;
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bytestream_output_enable_fe <= 1'b1;
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end else begin
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bytestream_data_out_fe <= bytestream_data_out;
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bytestream_valid_out_fe <= bytestream_valid_out;
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bytestream_direction_fe <= bytestream_direction;
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bytestream_output_enable_fe <= bytestream_output_enable;
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end
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end
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//----------------------------------------------------------------------------
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// wire assignment
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//----------------------------------------------------------------------------
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// 5 unused, 10 used, 1 unused and 4 used signals
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assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe};
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assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} };
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assign bytestream_valid_in = gpio_in[13];
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assign bytestream_data_in = gpio_in[12:5];
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//----------------------------------------------------------------------------
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// version_info
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//----------------------------------------------------------------------------
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// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
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assign version_info = build_component_versions(
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DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
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build_version(
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DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
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DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
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DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
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build_version(
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DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
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DB_GPIO_IFC_CURRENT_VERSION_MINOR,
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DB_GPIO_IFC_CURRENT_VERSION_BUILD));
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="VERSIONING_REGS_REGMAP">
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// <group name="VERSIONING_CONSTANTS">
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// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
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// <info>
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// Daughterboard GPIO interface.{BR/}
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// For guidance on when to update these revision numbers,
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// please refer to the register map documentation accordingly:
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// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
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// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
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// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
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// </info>
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// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
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// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
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// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
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// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
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// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
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// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
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// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x20110616"/>
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// </enumeratedtype>
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// </group>
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//</regmap>
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//XmlParse xml_off
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