b210-k7-fpga/top/n3xx/dboards/rh/cpld at 95c58d5ed6d1e71f9848a74a482fd4abc64cb922 - b210-k7-fpga - git.miegl.cz

miegl/b210-k7-fpga

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Humberto Jimenez 95c58d5ed6 fpga: n3xx: rh: cpld: Refactor CPLD build process

Original-commit: 739b37ba40e7aba288ed781922aa8fa3b1bfc16e

2022-01-25 18:28:57 -07:00

..

fpga: n3xx: rh: cpld: Refactor CPLD build process

2022-01-25 18:28:57 -07:00

.gitignore

fpga: n3xx: rh: cpld: Refactor CPLD build process

2022-01-25 18:28:57 -07:00

Makefile

fpga: n3xx: rh: cpld: Refactor CPLD build process

2022-01-25 18:28:57 -07:00

Makefile.cpld.inc

fpga: n3xx: rh: cpld: Refactor CPLD build process

2022-01-25 18:28:57 -07:00

rh_tb.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

rhodium_gain_ctrl.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

rhodium_gain_table.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

rhodium_lo_gain.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

rhodium_top.sdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

rhodium_top.v

fpga: n3xx: rh: cpld: Refactor CPLD build process

2022-01-25 18:28:57 -07:00