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95c58d5ed6d1e71f9848a74a482fd4abc64cb922
b210-k7-fpga
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Humberto Jimenez
95c58d5ed6
fpga: n3xx: rh: cpld: Refactor CPLD build process
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Original-commit: 739b37ba40e7aba288ed781922aa8fa3b1bfc16e
2022-01-25 18:28:57 -07:00
..
cpld
fpga: n3xx: rh: cpld: Refactor CPLD build process
2022-01-25 18:28:57 -07:00
db_ifc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
db_clocks.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
db_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
db_timing.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx.v
fpga: n3xx: Fix timeout for timekeeper registers
2020-08-19 12:28:22 -05:00