61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
268 lines
11 KiB
Verilog
268 lines
11 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x4xx_versioning_regs
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//
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// Description:
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//
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// This module contains the motherboard registers for tracking
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// HDL components versions.
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//
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// This versioning module is comprised of up to 256 read-only registers,
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// which provide versioning information for up to 64 components (256/4).
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// Each component has 3 x 32-bit registers for the following purpose:
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// - Current version
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// - Oldest compatible version
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// - Last modified time stamp
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//
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// Note that in order to facilitate implementation, each component
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// allocates a 4th register address (Reserved) for future use.
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//
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// Allocation of the 64 addressable components is shown below.
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// This allocation determines the definition of COMPONENTS_INDEXES
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// in the register map documentation below.
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//
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// --- Common components ---
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// Reserved space for up to 24 components.
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// - FPGA
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// - MB CPLD interface
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// - RF core (db 0)
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// - RF core (db 1)
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// - GPIO interface (db 0)
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// - GPIO interface (db 1)
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//
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// --- UHD-specific components ---
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// Reserved space for up to 20 components.
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// - QSFP wrapper (port 0)
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// - QSFP wrapper (port 1)
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//
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// --- LV-specific components ---
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// Reserved space for up to 20 components.
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//
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// Parameters:
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//
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// REG_BASE : Base address to use for registers.
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//
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`default_nettype none
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module x4xx_versioning_regs #(
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parameter REG_BASE = 0
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) (
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// Slave ctrlport interface
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input wire s_ctrlport_clk,
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input wire s_ctrlport_rst,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b00,
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output reg [31:0] s_ctrlport_resp_data = {32 {1'bX}},
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// Version (Constant)
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// Each component consists of a 96-bit vector (refer to versioning_utils.vh)
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input wire [64*96-1:0] version_info
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);
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`include "regmap/versioning_regs_regmap_utils.vh"
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`include "regmap/versioning_utils.vh"
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`include "../../lib/rfnoc/core/ctrlport.vh"
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// 64 components * 4 registers * 4 addresses p/ register
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localparam REG_SIZE = MAX_NUM_OF_COMPONENTS*4*4;
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//--------------------------------------------------------------------
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// Versioning Registers
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// -------------------------------------------------------------------
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// Check that address is within this module's range.
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wire address_in_range = (s_ctrlport_req_addr >= REG_BASE) && (s_ctrlport_req_addr < REG_BASE + REG_SIZE);
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// Mask out 6 bits (64 components) to be able to compare all components
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// against the same base register address.
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wire [31:0] register_base_address = {s_ctrlport_req_addr[19:10], 6'b0, s_ctrlport_req_addr[3:0]};
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// Extract masked out bits from the address, which represent the
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// component that is being addressed (0-63) = 6 bits.
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wire [ 5:0] component_index = s_ctrlport_req_addr[9:4];
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// Obtain the indexed component's versions
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wire [COMPONENT_VERSIONS_SIZE-1:0] component_versions = get_component_versions(version_info, component_index);
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// Registers implementation
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always @ (posedge s_ctrlport_clk) begin
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if (s_ctrlport_rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_status <= 2'b00;
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s_ctrlport_resp_data <= {32 {1'bX}};
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end else begin
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// Write registers
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if (s_ctrlport_req_wr) begin
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// Do not acknowledge by default
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= 32'h0;
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// No writable registers
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// Acknowledge and provide error status if address is in range
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if (address_in_range) begin
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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end
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// Read registers
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end else if (s_ctrlport_req_rd) begin
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// Acknowledge by default
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= 32'h0;
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s_ctrlport_resp_status <= CTRL_STS_OKAY;
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case (register_base_address)
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// Each concatenated 96-bit vector contains 3 x 32-bit values:
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// [31: 0] -> Current version
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// [63:32] -> Oldest compatible version
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// [95:64] -> Last modified
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REG_BASE + CURRENT_VERSION(0): begin
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s_ctrlport_resp_data[VERSION_TYPE_SIZE-1:0] <= current_version(component_versions);
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end
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REG_BASE + OLDEST_COMPATIBLE_VERSION(0): begin
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s_ctrlport_resp_data[VERSION_TYPE_SIZE-1:0] <= oldest_compatible_version(component_versions);
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end
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REG_BASE + VERSION_LAST_MODIFIED(0): begin
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s_ctrlport_resp_data[TIMESTAMP_TYPE_SIZE-1:0] <= version_last_modified(component_versions);
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end
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// Do not acknowledge if address is not defined
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default: begin
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if (address_in_range) begin
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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// No response if out of range
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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endcase
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end else begin
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s_ctrlport_resp_ack <= 1'b0;
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end
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end
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//<regmap name="VERSIONING_REGS_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="VERSIONING_REGS">
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// <regtype name="VERSION_TYPE" size="32" attributes="Readable">
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// <bitfield name="MAJOR" range="31..23" initialvalue="0">
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// <info>
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// Major number (max = 511): an increase reflects a breaking change.{BR/}
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// <b>IMPORTANT!</b> @.MAJOR must always remain in sync between the component's
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// @.CURRENT_VERSION and @.OLDEST_COMPATIBLE_VERSION registers.{BR/}{BR/}
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// Update @.MAJOR when:
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// <li>the component has changed and requires a software changes as a result.
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// <li>the component's bitfields/registers have been modified or deleted.
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// <li>the component's bitfields/registers are initialized to different value (unexpected by software).
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// <li>new bitfields/registers are added that require software interaction for the component to operate.
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// </info>
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// </bitfield>
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// <bitfield name="MINOR" range="22..12" initialvalue="0">
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// <info>
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// Minor number (max = 2047): an increase reflects a non-breaking change that the driver should be aware of.{BR/}{BR/}
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// Update @.MINOR when:
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// <li>a new feature is added to the component, which does not conflict with the driver.
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// <li>minor implementation changes were made to the component which are worth tracking.
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// <li>the component has added new bitfields/registers that do not require software interaction
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// (i.e. the default value is 0 and writing 0 does not change behavior, assuming SW writes 0's to
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// previously undefined bits).
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// <li>@.MAJOR is updated (reset @.MINOR to 0).
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// </info>
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// </bitfield>
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// <bitfield name="BUILD" range="11..0" initialvalue="0">
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// <info>
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// Build number (max = 4095): an increase reflects a change in the source code that yields a new implementation,
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// but that should not impact the component's behavior {BR/}
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// Eventually, this number is intended to be automatically incremented for any new build.{BR/}{BR/}
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// Meanwhile, update @.BUILD when:
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// <li>the component's source code changes are not captured by @.MAJOR or @.MINOR.
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// <li>@.MINOR or @.MAJOR are updated (reset @.BUILD to 0).
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// </info>
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// </bitfield>
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// </regtype>
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// <regtype name="TIMESTAMP_TYPE" size="32" attributes="Readable">
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// <info>
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// Component's versions update time.{BR/}
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// This register provides the time stamp for the last modification to
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// the component's versions (current & oldest compatible).
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// The time stamp is provided in hexadecimal format: 0xYYMMDDHH.
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// </info>
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// <bitfield name="YY" range="31..24">
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// <info>This is the year number after 2000 (e.g. 2019 = 0x19).</info>
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// </bitfield>
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// <bitfield name="MM" range="23..16"/>
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// <bitfield name="DD" range="15..8"/>
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// <bitfield name="HH" range="7..0"/>
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// </regtype>
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// <regtype name="RESERVED_TYPE" size="32" attributes="Readable">
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// <info>
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// Reserved.
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// </info>
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// </regtype>
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//
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// <enumeratedtype name="COMPONENTS_INDEXES">
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// <info>
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// This enum contains indexes for all the components in the X410
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// (both common and app-specific) which version information is
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// desired to be available for compatibility tracking purposes.{BR/}
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// {table border="1"}
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// {tr}{th}Description{/th} {th}Index range{/th} {th}Max # of components{/th}{/tr}
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// {tr}{td}Common components{/td} {td}0 to 23{/td} {td}24{/td}{/tr}
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// {tr}{td}UHD-specific components{/td} {td}24 to 43{/td} {td}20{/td}{/tr}
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// {tr}{td}LV-specific components{/td} {td}44 to 63{/td} {td}20{/td}{/tr}
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// {/table}
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// </info>
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// <value name="FPGA_VERSION_INDEX" integer="0"/>
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// <value name="CPLD_IFC_INDEX" integer="1"/>
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// <value name="DB0_RF_CORE_INDEX" integer="2"/>
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// <value name="DB1_RF_CORE_INDEX" integer="3"/>
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// <value name="DB0_GPIO_IFC_INDEX" integer="4"/>
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// <value name="DB1_GPIO_IFC_INDEX" integer="5"/>
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// </enumeratedtype>
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//
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// <register name="CURRENT_VERSION" offset="0x0" count="64" step="16" typename="VERSION_TYPE">
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// <info>
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// Component's current version.{BR/}
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// This register contains the current component's version implemented in HDL.
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// The current version shall be used to detect a component being too
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// old for the driver/software:{BR/}
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// <b>SW oldest compatible version > Component's current version --> Component is too old.</b>
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// </info>
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// </register>
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// <register name="OLDEST_COMPATIBLE_VERSION" offset="0x4" count="64" step="16" typename="VERSION_TYPE">
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// <info>
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// Component's oldest compatible version.{BR/}
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// This register contains the oldest compatible component's version, that is the oldest
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// component's implementation that is compatible with the current implementation.{BR/}
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// The oldest compatible version shall be used to detect a component being too
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// new for the driver/software:{BR/}
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// <b>SW current version < Component's oldest compatible version --> Component is too new.</b>
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// </info>
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// </register>
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// <register name="VERSION_LAST_MODIFIED" offset="0x8" count="64" step="16" typename="TIMESTAMP_TYPE"/>
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// <register name="RESERVED" offset="0xC" count="64" step="16" typename="RESERVED_TYPE"/>
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//
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// </group>
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//</regmap>
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//XmlParse xml_off
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