206 lines
5.8 KiB
Verilog
206 lines
5.8 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module simple_gemac_tb;
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`include "eth_tasks.v"
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reg clk = 0;
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reg reset = 1;
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initial #1000 reset = 0;
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always #50 clk = ~clk;
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wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
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wire [7:0] GMII_RXD, GMII_TXD;
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wire rx_valid, rx_error, rx_ack;
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wire tx_ack, tx_valid, tx_error;
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wire [7:0] rx_data, tx_data;
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reg [15:0] pause_time;
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reg pause_req = 0;
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wire GMII_RX_CLK = GMII_GTX_CLK;
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reg [7:0] FORCE_DAT_ERR = 0;
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reg FORCE_ERR = 0;
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// Loopback
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assign GMII_RX_DV = GMII_TX_EN;
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assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR;
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assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR;
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wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
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wire [47:0] mcast_addr = 0;
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wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0;
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simple_gemac simple_gemac
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(.clk125(clk), .reset(reset),
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.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
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.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
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.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
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.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
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.pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
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.ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
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.pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
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.pass_pause(pass_pause), .pass_all(pass_all),
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.rx_clk(rx_clk), .rx_data(rx_data),
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.rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
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.tx_clk(tx_clk), .tx_data(tx_data),
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.tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
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);
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wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
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wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
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reg rx_ll_dst_rdy2 = 1;
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wire [7:0] rx_ll_data, rx_ll_data2;
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wire rx_ll_error, rx_ll_error2;
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rxmac_to_ll8 rx_adapt
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(.clk(clk), .reset(reset), .clear(0),
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.rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
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.ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
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.ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
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ll8_shortfifo rx_sfifo
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(.clk(clk), .reset(reset), .clear(0),
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.datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
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.error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
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.dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
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.error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
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wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
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reg tx_ll_sof2=0, tx_ll_eof2=0;
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reg tx_ll_src_rdy2 = 0;
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wire tx_ll_dst_rdy2;
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wire [7:0] tx_ll_data;
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reg [7:0] tx_ll_data2 = 0;
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wire tx_ll_error;
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wire tx_ll_error2 = 0;
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ll8_shortfifo tx_sfifo
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(.clk(clk), .reset(reset), .clear(clear),
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.datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
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.error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
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.dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
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.error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
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ll8_to_txmac ll8_to_txmac
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(.clk(clk), .reset(reset), .clear(clear),
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.ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
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.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
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.tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
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initial $dumpfile("simple_gemac_tb.vcd");
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initial $dumpvars(0,simple_gemac_tb);
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integer i;
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reg [7:0] pkt_rom[0:65535];
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reg [1023:0] ROMFile;
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initial
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for (i=0;i<65536;i=i+1)
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pkt_rom[i] <= 8'h0;
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initial
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begin
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@(negedge reset);
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repeat (10)
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@(posedge clk);
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SendFlowCtrl(16'h0007); // Send flow control
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@(posedge clk);
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#30000;
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@(posedge clk);
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SendFlowCtrl(16'h0009); // Increas flow control before it expires
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#10000;
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@(posedge clk);
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SendFlowCtrl(16'h0000); // Cancel flow control before it expires
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@(posedge clk);
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SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters
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repeat (10)
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@(posedge clk);
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SendPacketFromFile_ll8(60,0,0); // The rest are valid packets
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repeat (10)
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@(posedge clk);
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SendPacketFromFile_ll8(61,0,0);
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repeat (10)
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@(posedge clk);
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SendPacketFromFile_ll8(62,0,0);
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repeat (10)
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@(posedge clk);
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SendPacketFromFile_ll8(63,0,0);
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repeat (1)
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@(posedge clk);
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SendPacketFromFile_ll8(64,0,0);
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repeat (10)
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@(posedge clk);
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SendPacketFromFile_ll8(59,0,0);
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repeat (1)
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@(posedge clk);
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SendPacketFromFile_ll8(58,0,0);
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repeat (1)
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@(posedge clk);
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SendPacketFromFile_ll8(100,0,0);
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repeat (1)
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@(posedge clk);
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SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns
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repeat (1)
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@(posedge clk);
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SendPacketFromFile_ll8(100,0,30);
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#10000 $finish;
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end
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// Force a CRC error
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initial
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begin
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#90000;
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@(posedge clk);
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FORCE_DAT_ERR <= 8'h10;
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@(posedge clk);
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FORCE_DAT_ERR <= 8'h00;
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end
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// Force an RX_ER error (i.e. link loss)
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initial
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begin
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#116000;
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@(posedge clk);
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FORCE_ERR <= 1;
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@(posedge clk);
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FORCE_ERR <= 0;
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end
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// Cause receive fifo to fill, causing an RX overrun
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initial
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begin
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#126000;
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@(posedge clk);
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rx_ll_dst_rdy2 <= 0;
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repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows
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@(posedge clk);
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rx_ll_dst_rdy2 <= 1;
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end
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// Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
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// Still need to test: CRC errors on Pause Frames
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always @(posedge clk)
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if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
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begin
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if(rx_ll_sof2 & ~rx_ll_eof2)
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$display("RX-PKT-START %d",$time);
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$display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
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if(rx_ll_eof2 & ~rx_ll_sof2)
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$display("RX-PKT-END %d",$time);
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end
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endmodule // simple_gemac_tb
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