60 lines
1.6 KiB
Verilog
60 lines
1.6 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module rxmac_to_ll8
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(input clk, input reset, input clear,
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input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack,
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output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy );
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reg [2:0] xfer_state;
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localparam XFER_IDLE = 0;
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localparam XFER_ACTIVE = 1;
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localparam XFER_ERROR = 2;
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localparam XFER_ERROR2 = 3;
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localparam XFER_OVERRUN = 4;
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localparam XFER_OVERRUN2 = 5;
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assign ll_data = rx_data;
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assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
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| (xfer_state == XFER_ERROR)
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| (xfer_state == XFER_OVERRUN));
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assign ll_sof = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN));
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assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN));
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assign ll_error = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN);
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always @(posedge clk)
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if(reset | clear)
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xfer_state <= XFER_IDLE;
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else
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case(xfer_state)
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XFER_IDLE :
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if(rx_valid)
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xfer_state <= XFER_ACTIVE;
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XFER_ACTIVE :
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if(rx_error)
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xfer_state <= XFER_ERROR;
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else if(~rx_valid)
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xfer_state <= XFER_IDLE;
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else if(~ll_dst_rdy)
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xfer_state <= XFER_OVERRUN;
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XFER_ERROR :
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if(ll_dst_rdy)
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xfer_state <= XFER_ERROR2;
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XFER_ERROR2 :
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if(~rx_error)
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xfer_state <= XFER_IDLE;
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XFER_OVERRUN :
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if(ll_dst_rdy)
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xfer_state <= XFER_OVERRUN2;
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XFER_OVERRUN2 :
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if(~rx_valid)
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xfer_state <= XFER_IDLE;
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endcase // case (xfer_state)
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endmodule // rxmac_to_ll8
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