67 lines
1.9 KiB
Verilog
67 lines
1.9 KiB
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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// RX side of flow control -- when we are running out of RX space, send a PAUSE
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module flow_ctrl_rx
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(input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh,
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input rx_clk, input rx_reset, input [15:0] rx_fifo_space,
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input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req
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);
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// ******************************************************************************
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// Force our TX to send a PAUSE frame because our RX is nearly full
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// ******************************************************************************
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// RX Clock Domain
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reg xon, xoff;
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reg [21:0] countdown;
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wire [15:0] pause_low_thresh = pause_thresh;
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wire [15:0] pause_hi_thresh = 16'hFFFF;
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wire [21:0] pq_reduced = {pause_time,6'd0} - 1700;
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always @(posedge rx_clk)
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if(rx_reset)
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xoff <= 0;
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else
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xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh));
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always @(posedge rx_clk)
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if(rx_reset)
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xon <= 0;
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else
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xon <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh));
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always @(posedge rx_clk)
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if(rx_reset)
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countdown <= 0;
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else if(xoff)
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countdown <= pq_reduced;
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else if(xon)
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countdown <= 0;
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else if(countdown != 0)
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countdown <= countdown - 1;
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// Cross clock domains
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wire xon_tx, xoff_tx;
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oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx));
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oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx));
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always @(posedge tx_clk)
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if(xoff_tx)
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pause_time_req <= pause_time;
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else if(xon_tx)
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pause_time_req <= 0;
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always @(posedge tx_clk)
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if(tx_reset)
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pause_req <= 0;
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else
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pause_req <= xon_tx | xoff_tx;
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endmodule // flow_ctrl_rx
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