Files
b210-k7-fpga/lib/sim/source_flow_control/test_window/run_iverilog
T
Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00

17 lines
344 B
Plaintext
Executable File

iverilog -y . \
-D SIM_SCRIPT=true \
../../../vita/new_tx_tb.v \
-y ../../../vita/ \
-y ../../../fifo/ \
-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims/ \
-y ../../../control/ \
-y ../../../timing/ \
-y ../../../dsp/ \
/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/ \
-y ../../../../../usrp2/models/ \
-Wall \
-o new_tx_tb.exe
./new_tx_tb.exe