93 lines
2.2 KiB
Verilog
93 lines
2.2 KiB
Verilog
`timescale 1ns/1ps
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module cvita_insert_tlast_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("cvita_insert_tlast_tb.vcd");
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initial $dumpvars(0,cvita_insert_tlast_tb);
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task send_packet;
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input [63:0] data_start;
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input [31:0] len;
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begin
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if(len < 9)
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begin
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{i_tlast, i_tdata} <= { 1'b1, data_start[63:48],len[15:0], data_start[31:0] };
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i_tvalid <= 1;
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@(posedge clk);
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i_tvalid <= 0;
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end
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else
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begin
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{i_tlast, i_tdata} <= { 1'b0, data_start[63:48],len[15:0], data_start[31:0] };
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i_tvalid <= 1;
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@(posedge clk);
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repeat(((len-2)/2)-1+len[0])
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begin
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i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
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@(posedge clk);
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end
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i_tdata <= i_tdata + 64'h0000_0002_0000_0002;
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i_tlast <= 1;
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@(posedge clk);
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i_tvalid <= 1'b0;
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end // else: !if(len < 3)
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end
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endtask // send_packet
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initial
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begin
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#1000 reset = 0;
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#200000;
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$finish;
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end
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reg [63:0] i_tdata;
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reg i_tlast;
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reg i_tvalid;
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wire i_tready;
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wire [63:0] o_tdata;
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wire o_tlast, o_tvalid, o_tready, o_tlast_regen;
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initial
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begin
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i_tvalid <= 0;
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while(reset)
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@(posedge clk);
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@(posedge clk);
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send_packet(64'hA0000000_A0000001, 24);
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send_packet(64'hA0000000_A0000001, 20);
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send_packet(64'hA0000000_A0000001, 16);
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send_packet(64'hA0000000_A0000001, 12);
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send_packet(64'hA0000000_A0000001, 8);
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send_packet(64'hA0000000_A0000001, 4);
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send_packet(64'hA0000000_A0000001, 4);
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send_packet(64'hA0000000_A0000001, 8);
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send_packet(64'hA0000000_A0000001, 12);
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end // initial begin
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cvita_insert_tlast dut
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tlast(o_tlast_regen), .o_tvalid(o_tvalid), .o_tready(o_tready));
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assign o_tready = 1;
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always @(posedge clk)
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if(o_tvalid & o_tready)
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begin
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$display ("TLAST %x\t TLAST_REGEN %x",i_tlast, o_tlast_regen);
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if(i_tlast != o_tlast_regen)
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$display("ERROR!!!!!!");
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end
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endmodule // cvita_insert_tlast_tb
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