104 lines
4.2 KiB
Verilog
104 lines
4.2 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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module pcie_basic_regs (
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input clk,
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input reset,
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input [63:0] regi_tdata,
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input regi_tvalid,
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output regi_tready,
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output [63:0] rego_tdata,
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output rego_tvalid,
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input rego_tready,
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input [31:0] misc_status
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);
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localparam PCIE_FPGA_SIG_VAL = 32'h58333030; //X300 (ASCII)
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localparam PCIE_FPGA_COUNTER_FREQ = 32'h0A6E49C0; //175MHz
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localparam PCIE_REG_ADDR_MASK = 20'h001FF;
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localparam PCIE_FPGA_SIG_REG_ADDR = 20'h00000; //32-bit
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localparam PCIE_FPGA_COUNTER_LO_REG_ADDR = 20'h00004; //32-bit
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localparam PCIE_FPGA_COUNTER_HI_REG_ADDR = 20'h00008; //32-bit
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localparam PCIE_FPGA_COUNTER_FREQ_ADDR = 20'h0000C; //32-bit
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localparam PCIE_FPGA_SCRATCH0_ADDR = 20'h00010; //32-bit
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localparam PCIE_FPGA_SCRATCH1_ADDR = 20'h00014; //32-bit
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localparam PCIE_FPGA_MISC_STATUS_ADDR = 20'h00020; //32-bit
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localparam PCIE_FPGA_USR_SIG_REG_ADDR = 20'h00030; //128-bit
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wire regi_wr, regi_rd;
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wire [19:0] regi_addr, regi_addr_local;
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wire [31:0] regi_payload;
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reg [31:0] rego_payload;
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ioport2_msg_decode regi_decoder (
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.message(regi_tdata), .wr_request(regi_wr), .rd_request(regi_rd),
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.address(regi_addr), .data(regi_payload)
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);
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ioport2_msg_encode rego_encoder (
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.rd_response(1'b1), .data(rego_payload), .message(rego_tdata)
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);
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assign regi_tready = (regi_tvalid & regi_wr) | rego_tready;
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assign rego_tvalid = regi_tvalid & regi_rd;
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assign regi_addr_local = regi_addr & PCIE_REG_ADDR_MASK;
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//Counter counting bus_clk cycles
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reg [63:0] bus_counter;
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always @(posedge clk) begin
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if (reset) bus_counter <= 64'h0;
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else bus_counter <= bus_counter + 1;
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end
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//Scratch registers
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reg [63:0] scratch;
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always @(posedge clk) begin
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if (reset)
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scratch <= 64'h0;
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else if (regi_tvalid & regi_tready & regi_wr)
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if (regi_addr_local == PCIE_FPGA_SCRATCH0_ADDR)
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scratch[31:0] <= regi_payload;
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else if (regi_addr_local == PCIE_FPGA_SCRATCH1_ADDR)
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scratch[63:32] <= regi_payload;
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end
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//User signature register
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reg [127:0] usr_signature;
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always @(posedge clk) begin
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if (reset)
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usr_signature <= 128'h0;
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else if (regi_tvalid & regi_tready & regi_wr)
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if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00000))
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usr_signature[31:0] <= regi_payload;
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else if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00004))
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usr_signature[63:32] <= regi_payload;
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else if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00008))
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usr_signature[95:64] <= regi_payload;
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else if (regi_addr_local == (PCIE_FPGA_USR_SIG_REG_ADDR + 20'h0000C))
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usr_signature[127:96] <= regi_payload;
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end
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always @(*) begin
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case (regi_addr_local)
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PCIE_FPGA_SIG_REG_ADDR: rego_payload = PCIE_FPGA_SIG_VAL;
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PCIE_FPGA_COUNTER_LO_REG_ADDR: rego_payload = bus_counter[31:0];
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PCIE_FPGA_COUNTER_HI_REG_ADDR: rego_payload = bus_counter[63:32];
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PCIE_FPGA_COUNTER_FREQ_ADDR: rego_payload = PCIE_FPGA_COUNTER_FREQ;
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PCIE_FPGA_SCRATCH0_ADDR: rego_payload = scratch[31:0];
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PCIE_FPGA_SCRATCH1_ADDR: rego_payload = scratch[63:32];
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PCIE_FPGA_MISC_STATUS_ADDR: rego_payload = misc_status;
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PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00000: rego_payload = usr_signature[31:0];
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PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00004: rego_payload = usr_signature[63:32];
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PCIE_FPGA_USR_SIG_REG_ADDR + 20'h00008: rego_payload = usr_signature[95:64];
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PCIE_FPGA_USR_SIG_REG_ADDR + 20'h0000C: rego_payload = usr_signature[127:96];
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default: rego_payload = 32'hFFFFFFFF;
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endcase
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end
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endmodule
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