34 lines
735 B
Verilog
34 lines
735 B
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module acc
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#(parameter IWIDTH=16, OWIDTH=30)
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(input clk,
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input clear,
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input acc,
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input [IWIDTH-1:0] in,
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output reg [OWIDTH-1:0] out);
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wire [OWIDTH-1:0] in_signext;
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sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH))
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acc_signext (.in(in),.out(in_signext));
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// CLEAR & ~ACC --> clears the accumulator
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// CLEAR & ACC --> loads the accumulator
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// ~CLEAR & ACC --> accumulates
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// ~CLEAR & ~ACC --> hold
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wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
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wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
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wire [OWIDTH-1:0] sum_int = addend1 + addend2;
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always @(posedge clk)
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out <= sum_int;
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endmodule // acc
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