Andrew Moch 6606757fa7 fpga: lib: Update AxiLiteIf ...

This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.


Original-commit: 6ef642e3ac44c52b98b124f30dc84b1683859989

2020-07-31 11:55:47 -05:00

..

axi_lite.vh

fpga: lib: Add features to axi_lite.vh

2020-06-26 10:36:37 -05:00

AxiLiteIf.sv

fpga: lib: Update AxiLiteIf

2020-07-31 11:55:47 -05:00

Makefile.srcs

fpga: lib: Add interface and model for AXI4-Lite

2020-06-24 09:56:31 -05:00

PkgAxiLite.sv

fpga: lib: Add interface and model for AXI4-Lite

2020-06-24 09:56:31 -05:00