61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
21 lines
542 B
Verilog
21 lines
542 B
Verilog
module hbdec2(
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sclr, ce, rfd, rdy, data_valid, coef_we, nd, clk,
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coef_ld, dout_1, dout_2, din_1, din_2, coef_din
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)
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/* synthesis syn_black_box black_box_pad_pin="sclr,ce,rfd,rdy,data_valid,coef_we,nd,clk,coef_ld,dout_1[47:0],dout_2[47:0],din_1[23:0],din_2[23:0],coef_din[17:0]" */;
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input sclr;
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input ce;
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output rfd;
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output rdy;
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output data_valid;
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input coef_we;
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input nd;
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input clk;
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input coef_ld;
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output [46:0]dout_1;
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output [46:0]dout_2;
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input [23:0]din_1;
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input [23:0]din_2;
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input [17:0]coef_din;
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endmodule
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