Wade Fife
f1d3374e50
This renames e31x_rfnoc_image_core.* to e310_rfnoc_image_core.*. This makes the naming consistent with the rest of the build process (which uses "e310" for all variants of e31x) and fixes an issue in which the wrong file name was used by rfnoc_image_builder. Original-commit: bbd43b16e18ef0a0311ddf4635cbd29c4ac3c367
55 lines
2.8 KiB
YAML
55 lines
2.8 KiB
YAML
# General parameters
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# -----------------------------------------
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schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file
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copyright: 'Ettus Research, A National Instruments Brand' # Copyright information used in file headers
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license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used in file headers
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version: 1.0 # File version
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rfnoc_version: 1.0 # RFNoC protocol version
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chdr_width: 64 # Bit width of the CHDR bus for this image
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device: 'e310'
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default_target: 'E310_SG3'
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# A list of all stream endpoints in design
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# ----------------------------------------
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stream_endpoints:
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ep0: # Stream endpoint name
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ctrl: True # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size: 16384 # Ingress buffer size for data
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ep1: # Stream endpoint name
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ctrl: False # Endpoint passes control traffic
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data: True # Endpoint passes data traffic
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buff_size: 16384 # Ingress buffer size for data
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# A list of all NoC blocks in design
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# ----------------------------------
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noc_blocks:
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radio0: # NoC block name
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block_desc: 'radio_2x64.yml' # Block device descriptor
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# A list of all static connections in design
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# ------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect
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# - srcport = Port on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Port on the destination block to connect
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connections:
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- { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 }
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- { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 }
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- { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 }
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- { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 }
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- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport: ctrlport_radio }
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- { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport: x300_radio }
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- { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport: time_keeper }
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# A list of all clock domain connections in design
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# ------------------------------------------------
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# Format: A list of connection maps (list of key-value pairs) with the following keys
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# - srcblk = Source block to connect (Always "_device"_)
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# - srcport = Clock domain on the source block to connect
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# - dstblk = Destination block to connect
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# - dstport = Clock domain on the destination block to connect
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clk_domains:
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- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
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