Wade Fife
3bc803026b
This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits. Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
180 lines
6.6 KiB
Verilog
180 lines
6.6 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_timer
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//
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// Description:
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// The Control-Port timer module converts an asynchronous timed
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// transaction into a synchronous blocking transaction. This
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// module will use the input req_has_time and req_time fields and
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// produce an output transaction that will execute when the requested
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// time is current. The module does not pass the has_time and time
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// signals out because they are no longer relevant. The current time
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// is an input to this module, and must be a monotonic counter that
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// updates every time the time strobe is asserted.
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//
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// Parameters:
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// - EXEC_LATE_CMDS : If EXEC_LATE_CMDS = 0 and a command is late, then a
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// TSERR response is returned. If EXEC_LATE_CMDS = 1, then
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// a late command will be passed to the output as if it
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// were on time.
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//
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// Signals:
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// - time_now* : The time_now signal is the current time and the stb
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// signal indicates that the time_now is valid.
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// - time_ignore_bits : Number of least-significant bits to ignore when doing
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// time comparisons. This should be a constant.
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// - s_ctrlport_* : The slave Control-Port bus.
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// This must have the has_time and time signals.
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// - m_ctrlport_* : The master Control-Port bus.
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// This will not have the has_time and time signals.
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module ctrlport_timer #(
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parameter [0:0] EXEC_LATE_CMDS = 1
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)(
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// Clocks and Resets
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input wire clk,
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input wire rst,
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// Timestamp (synchronous to clk)
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input wire [63:0] time_now,
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input wire time_now_stb,
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input wire [3:0] time_ignore_bits,
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// Control Port Master (Request)
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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// Control Port Slave (Response)
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output wire s_ctrlport_resp_ack,
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output wire [1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// Control Port Master (Request)
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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output wire [3:0] m_ctrlport_req_byte_en,
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// Control Port Master (Response)
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input wire m_ctrlport_resp_ack,
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input wire [1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_axis_ctrl_utils.vh"
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// Control triggers:
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// - pending: A command is waiting on the input port
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// - has_time: The command is timed
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// - on_time: The timed command is due for execution (on time)
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// - late: The timed command is late
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// - exec: Execute the command (pass it to the output)
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// - consume: Consume the input command
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reg pending, has_time, on_time, late;
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wire exec, consume, valid;
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// Cached values for input command
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wire cached_req_wr, cached_req_rd;
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wire [19:0] cached_req_addr;
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wire [31:0] cached_req_data;
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wire [3:0] cached_req_byte_en;
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wire cached_req_has_time;
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wire [63:0] cached_req_time;
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wire cached_req_valid;
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axi_fifo_flop #(.WIDTH(1+1+20+32+4+1+64)) req_cache_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata({s_ctrlport_req_wr, s_ctrlport_req_rd, s_ctrlport_req_addr, s_ctrlport_req_data,
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s_ctrlport_req_byte_en, s_ctrlport_req_has_time, s_ctrlport_req_time}),
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.i_tvalid(s_ctrlport_req_wr | s_ctrlport_req_rd), .i_tready(),
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.o_tdata({cached_req_wr, cached_req_rd, cached_req_addr, cached_req_data,
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cached_req_byte_en, cached_req_has_time, cached_req_time}),
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.o_tvalid(cached_req_valid), .o_tready(consume),
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.occupied(), .space()
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);
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// Create a mask so that we can ignore the lower time_ignore_bits of the time.
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wire [63:0] mask = (~64'd0 << time_ignore_bits);
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// Pipeline registers
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reg has_time_0;
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reg has_time_1;
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reg valid_0;
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reg valid_1;
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reg [63:0] time_0;
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reg time_stb_1, time_stb_0;
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reg [63:0] req_time_0;
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reg on_time_1;
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reg late_1;
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// This always block pipelines the time comparisons and other condition
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// checks, so we don't have a long combinational path here. This adds some
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// delay to the execution of timed commands, but this block is not intended
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// for cycle-accurate register updates.
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always @(posedge clk) begin
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if (rst || consume) begin
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has_time_0 <= 'bX;
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time_stb_0 <= 'bX;
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time_0 <= 'bX;
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req_time_0 <= 'bX;
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has_time_1 <= 'bX;
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time_stb_1 <= 'bX;
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on_time_1 <= 'bX;
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late_1 <= 'bX;
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has_time <= 'bX;
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on_time <= 'bX;
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// These need to be zeroed, to clear the pipeline:
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valid_0 <= 1'b0;
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valid_1 <= 1'b0;
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pending <= 1'b0;
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late <= 1'b0;
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end else begin
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// Stage 0
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valid_0 <= cached_req_valid;
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has_time_0 <= cached_req_has_time;
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time_stb_0 <= time_now_stb;
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time_0 <= time_now & mask;
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req_time_0 <= cached_req_time & mask;
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// Stage 1
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valid_1 <= valid_0;
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has_time_1 <= has_time_0;
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time_stb_1 <= time_stb_0;
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on_time_1 <= req_time_0 == time_0;
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late_1 <= req_time_0 < time_0;
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// Stage 3
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pending <= valid_1;
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has_time <= has_time_1;
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on_time <= valid_1 && has_time_1 && time_stb_1 && on_time_1;
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late <= valid_1 && has_time_1 && time_stb_1 && late_1;
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end
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end
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// Logic to pass cmd forward
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assign exec = pending && (!has_time || on_time || (EXEC_LATE_CMDS && late));
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assign consume = exec || late;
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assign m_ctrlport_req_wr = cached_req_wr & exec;
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assign m_ctrlport_req_rd = cached_req_rd & exec;
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assign m_ctrlport_req_addr = cached_req_addr;
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assign m_ctrlport_req_data = cached_req_data;
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assign m_ctrlport_req_byte_en = cached_req_byte_en;
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wire [1:0] resp_status = (late && !exec) ? AXIS_CTRL_STS_TSERR : m_ctrlport_resp_status;
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axi_fifo_flop #(.WIDTH(2+32)) resp_cache_i (
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.clk(clk), .reset(rst), .clear(1'b0),
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.i_tdata({resp_status, m_ctrlport_resp_data}),
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.i_tvalid(m_ctrlport_resp_ack || (late && !exec)), .i_tready(),
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.o_tdata({s_ctrlport_resp_status, s_ctrlport_resp_data}),
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.o_tvalid(s_ctrlport_resp_ack), .o_tready(s_ctrlport_resp_ack),
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.occupied(), .space()
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);
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endmodule // ctrlport_timer
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