Wade Fife 7dc93d0e8c fpga: e320 Change MIG arbitration to RD_PRI_REG ...

Original-commit: 2a27f72f86e74c569e5ea158a5ca9cde68c41a97

2022-11-08 08:20:48 -06:00

..

aurora_64b66b_pcs_pma

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

axi64_4k_2clk_fifo

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

axi64_8k_2clk_fifo

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

axi_eth_dma

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

axi_intercon_4x64_256_bd

fpga: Update makefiles to allow parallel FPGA builds

2022-08-16 10:16:22 -05:00

ddr3_32bit

fpga: e320 Change MIG arbitration to RD_PRI_REG

2022-11-08 08:20:48 -06:00

e320_ps_bd

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

fifo_4k_2clk

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

fifo_short_2clk

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

one_gig_eth_pcs_pma

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

ten_gig_eth_pcs_pma

fpga: e320: Upgrade to Vivado 2021.1

2022-08-25 13:55:30 -05:00

Makefile.inc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00