61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
639 lines
28 KiB
Verilog
639 lines
28 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: cpld_interface.v
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//
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// Description:
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//
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// This module comprises the logic on the FPGA to connect with the
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// motherboard CPLD.
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//
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// As a first step each request source is transferred to PRC domain.
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// Timestamps are removed in the timer modules. All requests are bundled in
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// one combiner and then split / decoded across all targets. By inserting of
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// ctrlport termination modules a ctrlport answer will be available for all
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// addresses to avoid blocking the main ctrlport combiner.
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//
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`default_nettype none
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module cpld_interface (
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// Clocks
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire pll_ref_clk,
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input wire radio_clk,
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// Reset (domain: pll_ref_clk)
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input wire ctrlport_rst,
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// Timestamp (domain: radio_clk)
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input wire [63:0] radio_time,
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input wire radio_time_stb,
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input wire [ 3:0] time_ignore_bits,
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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input wire [16:0] s_axi_awaddr,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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input wire [31:0] s_axi_wdata,
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input wire [ 3:0] s_axi_wstrb,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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output wire[ 1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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input wire [16:0] s_axi_araddr,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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output wire [31:0] s_axi_rdata,
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output wire [ 1:0] s_axi_rresp,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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// Control port from / to application (domain: radio_clk)
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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// SPI Bus to connect to MB CPLD
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output wire [ 1:0] ss,
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output wire sclk,
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output wire mosi,
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input wire miso,
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// QSFP port LED (domain: any)
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input wire [ 3:0] qsfp0_led_active,
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input wire [ 3:0] qsfp0_led_link,
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input wire [ 3:0] qsfp1_led_active,
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input wire [ 3:0] qsfp1_led_link,
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// iPass present signals
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input wire [ 1:0] ipass_present_n,
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// Version (Constant)
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output wire [95:0] version_info
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);
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`include "../../lib/rfnoc/core/ctrlport.vh"
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`include "regmap/pl_cpld_regmap_utils.vh"
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`include "cpld/regmap/mb_cpld_pl_regmap_utils.vh"
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`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
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//---------------------------------------------------------------------------
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// Internal clocks and resets
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//---------------------------------------------------------------------------
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wire s_axi_areset;
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wire ctrlport_clk;
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assign s_axi_areset = ~s_axi_aresetn;
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assign ctrlport_clk = pll_ref_clk;
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//---------------------------------------------------------------------------
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// Timestamp synchronization
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//---------------------------------------------------------------------------
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reg [ 3:0] radio_time_stb_shift_reg;
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wire radio_time_stb_prc;
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reg [63:0] radio_time_prc;
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// radio_clk and pll_ref_clk are synchronous clocks with an integer
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// multiplier <= 4.
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//
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// A simple register can be used to capture the latest timestamp the strobe
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// pulse is preserved for up to 4 clock cycles and used in pll_ref_clk domain
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// to driver timers.
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always @(posedge radio_clk) begin
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radio_time_stb_shift_reg <= {radio_time_stb_shift_reg[2:0], radio_time_stb};
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if (radio_time_stb) begin
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radio_time_prc <= radio_time;
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end
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end
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assign radio_time_stb_prc = | radio_time_stb_shift_reg;
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//---------------------------------------------------------------------------
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// MPM Endpoint connection
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//---------------------------------------------------------------------------
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// Translate AXI lite to control port.
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// Timeout based on the 40 MHz AXI clock is about 0.839 seconds.
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wire [19:0] mpm_endpoint_ctrlport_axi_clk_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_axi_clk_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_axi_clk_req_data;
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wire mpm_endpoint_ctrlport_axi_clk_req_has_time;
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wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_portid;
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wire mpm_endpoint_ctrlport_axi_clk_req_rd;
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wire [15:0] mpm_endpoint_ctrlport_axi_clk_req_rem_epid;
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wire [ 9:0] mpm_endpoint_ctrlport_axi_clk_req_rem_portid;
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wire [63:0] mpm_endpoint_ctrlport_axi_clk_req_time;
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wire mpm_endpoint_ctrlport_axi_clk_req_wr;
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wire mpm_endpoint_ctrlport_axi_clk_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_axi_clk_resp_data;
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wire [ 1:0] mpm_endpoint_ctrlport_axi_clk_resp_status;
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axil_ctrlport_master #(
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.TIMEOUT (25),
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.AXI_AWIDTH (17),
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.CTRLPORT_AWIDTH (17)
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) mpm_endpoint (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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.m_ctrlport_req_wr (mpm_endpoint_ctrlport_axi_clk_req_wr),
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.m_ctrlport_req_rd (mpm_endpoint_ctrlport_axi_clk_req_rd),
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.m_ctrlport_req_addr (mpm_endpoint_ctrlport_axi_clk_req_addr),
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.m_ctrlport_req_portid (mpm_endpoint_ctrlport_axi_clk_req_portid),
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.m_ctrlport_req_rem_epid (mpm_endpoint_ctrlport_axi_clk_req_rem_epid),
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.m_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
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.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
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.m_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data)
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);
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// Transfer AXI clock based MPM endpoint control port request to pll_ref_clk
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// domain.
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wire [19:0] mpm_endpoint_ctrlport_pll_clk_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_pll_clk_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_pll_clk_req_data;
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wire mpm_endpoint_ctrlport_pll_clk_req_has_time;
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wire mpm_endpoint_ctrlport_pll_clk_req_rd;
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wire [63:0] mpm_endpoint_ctrlport_pll_clk_req_time;
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wire mpm_endpoint_ctrlport_pll_clk_req_wr;
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wire mpm_endpoint_ctrlport_pll_clk_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_pll_clk_resp_data;
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wire [ 1:0] mpm_endpoint_ctrlport_pll_clk_resp_status;
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ctrlport_clk_cross ctrlport_clk_cross_mpm (
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.rst (s_axi_areset),
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.s_ctrlport_clk (s_axi_aclk),
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.s_ctrlport_req_wr (mpm_endpoint_ctrlport_axi_clk_req_wr),
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.s_ctrlport_req_rd (mpm_endpoint_ctrlport_axi_clk_req_rd),
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.s_ctrlport_req_addr (mpm_endpoint_ctrlport_axi_clk_req_addr),
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.s_ctrlport_req_portid (mpm_endpoint_ctrlport_axi_clk_req_portid),
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.s_ctrlport_req_rem_epid (mpm_endpoint_ctrlport_axi_clk_req_rem_epid),
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.s_ctrlport_req_rem_portid (mpm_endpoint_ctrlport_axi_clk_req_rem_portid),
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.s_ctrlport_req_data (mpm_endpoint_ctrlport_axi_clk_req_data),
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.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_axi_clk_req_byte_en),
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.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_axi_clk_req_has_time),
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.s_ctrlport_req_time (mpm_endpoint_ctrlport_axi_clk_req_time),
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.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_axi_clk_resp_ack),
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.s_ctrlport_resp_status (mpm_endpoint_ctrlport_axi_clk_resp_status),
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.s_ctrlport_resp_data (mpm_endpoint_ctrlport_axi_clk_resp_data),
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.m_ctrlport_clk (ctrlport_clk),
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.m_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
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.m_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
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.m_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
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.m_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
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.m_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data)
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);
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// Apply time of ControlPort request to MPM endpoint request.
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wire [19:0] mpm_endpoint_ctrlport_req_addr;
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wire [ 3:0] mpm_endpoint_ctrlport_req_byte_en;
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wire [31:0] mpm_endpoint_ctrlport_req_data;
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wire mpm_endpoint_ctrlport_req_rd;
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wire mpm_endpoint_ctrlport_req_wr;
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wire mpm_endpoint_ctrlport_resp_ack;
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wire [31:0] mpm_endpoint_ctrlport_resp_data;
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wire [ 1:0] mpm_endpoint_ctrlport_resp_status;
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ctrlport_timer #(
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.EXEC_LATE_CMDS (1)
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) ctrlport_timer_mpm (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.time_now (radio_time_prc),
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.time_now_stb (radio_time_stb_prc),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (mpm_endpoint_ctrlport_pll_clk_req_wr),
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.s_ctrlport_req_rd (mpm_endpoint_ctrlport_pll_clk_req_rd),
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.s_ctrlport_req_addr (mpm_endpoint_ctrlport_pll_clk_req_addr),
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.s_ctrlport_req_data (mpm_endpoint_ctrlport_pll_clk_req_data),
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.s_ctrlport_req_byte_en (mpm_endpoint_ctrlport_pll_clk_req_byte_en),
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.s_ctrlport_req_has_time (mpm_endpoint_ctrlport_pll_clk_req_has_time),
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.s_ctrlport_req_time (mpm_endpoint_ctrlport_pll_clk_req_time),
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.s_ctrlport_resp_ack (mpm_endpoint_ctrlport_pll_clk_resp_ack),
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.s_ctrlport_resp_status (mpm_endpoint_ctrlport_pll_clk_resp_status),
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.s_ctrlport_resp_data (mpm_endpoint_ctrlport_pll_clk_resp_data),
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.m_ctrlport_req_wr (mpm_endpoint_ctrlport_req_wr),
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.m_ctrlport_req_rd (mpm_endpoint_ctrlport_req_rd),
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.m_ctrlport_req_addr (mpm_endpoint_ctrlport_req_addr),
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.m_ctrlport_req_data (mpm_endpoint_ctrlport_req_data),
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.m_ctrlport_req_byte_en (mpm_endpoint_ctrlport_req_byte_en),
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.m_ctrlport_resp_ack (mpm_endpoint_ctrlport_resp_ack),
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.m_ctrlport_resp_status (mpm_endpoint_ctrlport_resp_status),
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.m_ctrlport_resp_data (mpm_endpoint_ctrlport_resp_data)
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);
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//---------------------------------------------------------------------------
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// User Application Request
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//---------------------------------------------------------------------------
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// Transfer request to pll_ref_clk domain.
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wire [19:0] app_ctrlport_pll_clk_req_addr;
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wire [ 3:0] app_ctrlport_pll_clk_req_byte_en;
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wire [31:0] app_ctrlport_pll_clk_req_data;
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wire app_ctrlport_pll_clk_req_has_time;
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wire app_ctrlport_pll_clk_req_rd;
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wire [63:0] app_ctrlport_pll_clk_req_time;
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wire app_ctrlport_pll_clk_req_wr;
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wire app_ctrlport_pll_clk_resp_ack;
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wire [31:0] app_ctrlport_pll_clk_resp_data;
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wire [ 1:0] app_ctrlport_pll_clk_resp_status;
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ctrlport_clk_cross ctrlport_clk_cross_app (
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.rst (ctrlport_rst),
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.s_ctrlport_clk (radio_clk),
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.s_ctrlport_req_wr (s_ctrlport_req_wr),
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.s_ctrlport_req_rd (s_ctrlport_req_rd),
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.s_ctrlport_req_addr (s_ctrlport_req_addr),
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.s_ctrlport_req_portid (),
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.s_ctrlport_req_rem_epid (),
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.s_ctrlport_req_rem_portid (),
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.s_ctrlport_req_data (s_ctrlport_req_data),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
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.s_ctrlport_req_time (s_ctrlport_req_time),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
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.s_ctrlport_resp_status (s_ctrlport_resp_status),
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.s_ctrlport_resp_data (s_ctrlport_resp_data),
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.m_ctrlport_clk (ctrlport_clk),
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.m_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
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.m_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
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.m_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
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.m_ctrlport_req_portid (),
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.m_ctrlport_req_rem_epid (),
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.m_ctrlport_req_rem_portid (),
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.m_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
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.m_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
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.m_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
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.m_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
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.m_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
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.m_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
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.m_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data)
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);
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// Apply timing to application based ControlPort request.
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wire [19:0] app_ctrlport_req_addr;
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wire [ 3:0] app_ctrlport_req_byte_en;
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wire [31:0] app_ctrlport_req_data;
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wire app_ctrlport_req_rd;
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wire app_ctrlport_req_wr;
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wire app_ctrlport_resp_ack;
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wire [31:0] app_ctrlport_resp_data;
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wire [ 1:0] app_ctrlport_resp_status;
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ctrlport_timer #(
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.EXEC_LATE_CMDS (1)
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) ctrlport_timer_app (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.time_now (radio_time_prc),
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.time_now_stb (radio_time_stb_prc),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (app_ctrlport_pll_clk_req_wr),
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.s_ctrlport_req_rd (app_ctrlport_pll_clk_req_rd),
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.s_ctrlport_req_addr (app_ctrlport_pll_clk_req_addr),
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.s_ctrlport_req_data (app_ctrlport_pll_clk_req_data),
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.s_ctrlport_req_byte_en (app_ctrlport_pll_clk_req_byte_en),
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.s_ctrlport_req_has_time (app_ctrlport_pll_clk_req_has_time),
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.s_ctrlport_req_time (app_ctrlport_pll_clk_req_time),
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.s_ctrlport_resp_ack (app_ctrlport_pll_clk_resp_ack),
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.s_ctrlport_resp_status (app_ctrlport_pll_clk_resp_status),
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.s_ctrlport_resp_data (app_ctrlport_pll_clk_resp_data),
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.m_ctrlport_req_wr (app_ctrlport_req_wr),
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.m_ctrlport_req_rd (app_ctrlport_req_rd),
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.m_ctrlport_req_addr (app_ctrlport_req_addr),
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.m_ctrlport_req_data (app_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en (app_ctrlport_req_byte_en),
|
|
.m_ctrlport_resp_ack (app_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status (app_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data (app_ctrlport_resp_data)
|
|
);
|
|
|
|
//---------------------------------------------------------------------------
|
|
// QSFP LED Controller
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [19:0] led_ctrlport_req_addr;
|
|
wire [ 3:0] led_ctrlport_req_byte_en;
|
|
wire [31:0] led_ctrlport_req_data;
|
|
wire led_ctrlport_req_rd;
|
|
wire led_ctrlport_req_wr;
|
|
wire led_ctrlport_resp_ack;
|
|
wire [31:0] led_ctrlport_resp_data;
|
|
wire [ 1:0] led_ctrlport_resp_status;
|
|
|
|
qsfp_led_controller
|
|
# (.LED_REGISTER_ADDRESS(MB_CPLD + PL_REGISTERS + LED_REGISTER))
|
|
qsfp_led_controller_i (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.m_ctrlport_req_wr (led_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd (led_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (led_ctrlport_req_addr),
|
|
.m_ctrlport_req_data (led_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en (led_ctrlport_req_byte_en),
|
|
.m_ctrlport_resp_ack (led_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status (led_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data (led_ctrlport_resp_data),
|
|
.qsfp0_led_active (qsfp0_led_active),
|
|
.qsfp0_led_link (qsfp0_led_link),
|
|
.qsfp1_led_active (qsfp1_led_active),
|
|
.qsfp1_led_link (qsfp1_led_link));
|
|
|
|
//---------------------------------------------------------------------------
|
|
// iPass present controller
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [19:0] ipass_ctrlport_req_addr;
|
|
wire [ 3:0] ipass_ctrlport_req_byte_en;
|
|
wire [31:0] ipass_ctrlport_req_data;
|
|
wire ipass_ctrlport_req_rd;
|
|
wire ipass_ctrlport_req_wr;
|
|
wire ipass_ctrlport_resp_ack;
|
|
wire [31:0] ipass_ctrlport_resp_data;
|
|
wire [ 1:0] ipass_ctrlport_resp_status;
|
|
|
|
wire ipass_enable;
|
|
|
|
ipass_present_controller ipass_present_controller_i (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.m_ctrlport_req_wr (ipass_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd (ipass_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (ipass_ctrlport_req_addr),
|
|
.m_ctrlport_req_data (ipass_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en (ipass_ctrlport_req_byte_en),
|
|
.m_ctrlport_resp_ack (ipass_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status (ipass_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data (ipass_ctrlport_resp_data),
|
|
.enable (ipass_enable),
|
|
.ipass_present_n (ipass_present_n)
|
|
);
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Combine all incoming combiner requests and provide to targets
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [19:0] m_ctrlport_req_addr;
|
|
wire [31:0] m_ctrlport_req_data;
|
|
wire m_ctrlport_req_rd;
|
|
wire m_ctrlport_req_wr;
|
|
wire m_ctrlport_resp_ack;
|
|
wire [31:0] m_ctrlport_resp_data;
|
|
wire [ 1:0] m_ctrlport_resp_status;
|
|
|
|
ctrlport_combiner #(
|
|
.NUM_MASTERS (4),
|
|
.PRIORITY (1)
|
|
) ctrlport_combiner_i (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.s_ctrlport_req_wr ({ipass_ctrlport_req_wr, led_ctrlport_req_wr, mpm_endpoint_ctrlport_req_wr, app_ctrlport_req_wr}),
|
|
.s_ctrlport_req_rd ({ipass_ctrlport_req_rd, led_ctrlport_req_rd, mpm_endpoint_ctrlport_req_rd, app_ctrlport_req_rd}),
|
|
.s_ctrlport_req_addr ({ipass_ctrlport_req_addr, led_ctrlport_req_addr, mpm_endpoint_ctrlport_req_addr, app_ctrlport_req_addr}),
|
|
.s_ctrlport_req_portid (),
|
|
.s_ctrlport_req_rem_epid (),
|
|
.s_ctrlport_req_rem_portid (),
|
|
.s_ctrlport_req_data ({ipass_ctrlport_req_data, led_ctrlport_req_data, mpm_endpoint_ctrlport_req_data, app_ctrlport_req_data}),
|
|
.s_ctrlport_req_byte_en ({ipass_ctrlport_req_byte_en, led_ctrlport_req_byte_en, mpm_endpoint_ctrlport_req_byte_en, app_ctrlport_req_byte_en}),
|
|
.s_ctrlport_req_has_time (),
|
|
.s_ctrlport_req_time (),
|
|
.s_ctrlport_resp_ack ({ipass_ctrlport_resp_ack, led_ctrlport_resp_ack, mpm_endpoint_ctrlport_resp_ack, app_ctrlport_resp_ack}),
|
|
.s_ctrlport_resp_status ({ipass_ctrlport_resp_status, led_ctrlport_resp_status, mpm_endpoint_ctrlport_resp_status, app_ctrlport_resp_status}),
|
|
.s_ctrlport_resp_data ({ipass_ctrlport_resp_data, led_ctrlport_resp_data, mpm_endpoint_ctrlport_resp_data, app_ctrlport_resp_data}),
|
|
.m_ctrlport_req_wr (m_ctrlport_req_wr),
|
|
.m_ctrlport_req_rd (m_ctrlport_req_rd),
|
|
.m_ctrlport_req_addr (m_ctrlport_req_addr),
|
|
.m_ctrlport_req_portid (),
|
|
.m_ctrlport_req_rem_epid (),
|
|
.m_ctrlport_req_rem_portid (),
|
|
.m_ctrlport_req_data (m_ctrlport_req_data),
|
|
.m_ctrlport_req_byte_en (),
|
|
.m_ctrlport_req_has_time (),
|
|
.m_ctrlport_req_time (),
|
|
.m_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
|
.m_ctrlport_resp_status (m_ctrlport_resp_status),
|
|
.m_ctrlport_resp_data (m_ctrlport_resp_data)
|
|
);
|
|
|
|
|
|
// Split for CPLD facing requests and others.
|
|
wire [19:0] base_reg_ctrlport_req_addr;
|
|
wire [31:0] base_reg_ctrlport_req_data;
|
|
wire base_reg_ctrlport_req_rd;
|
|
wire base_reg_ctrlport_req_wr;
|
|
wire base_reg_ctrlport_resp_ack;
|
|
wire [31:0] base_reg_ctrlport_resp_data;
|
|
wire [ 1:0] base_reg_ctrlport_resp_status;
|
|
|
|
wire [19:0] spi_master_ctrlport_req_addr;
|
|
wire [31:0] spi_master_ctrlport_req_data;
|
|
wire spi_master_ctrlport_req_rd;
|
|
wire spi_master_ctrlport_req_wr;
|
|
wire spi_master_ctrlport_resp_ack;
|
|
wire [31:0] spi_master_ctrlport_resp_data;
|
|
wire [ 1:0] spi_master_ctrlport_resp_status;
|
|
|
|
wire [19:0] unused_fpga_intermediate_ctrlport_req_addr;
|
|
wire [31:0] unused_fpga_intermediate_ctrlport_req_data;
|
|
wire unused_fpga_intermediate_ctrlport_req_rd;
|
|
wire unused_fpga_intermediate_ctrlport_req_wr;
|
|
wire unused_fpga_intermediate_ctrlport_resp_ack;
|
|
wire [31:0] unused_fpga_intermediate_ctrlport_resp_data;
|
|
wire [ 1:0] unused_fpga_intermediate_ctrlport_resp_status;
|
|
|
|
wire [19:0] unused_fpga_msbs_ctrlport_req_addr;
|
|
wire [31:0] unused_fpga_msbs_ctrlport_req_data;
|
|
wire unused_fpga_msbs_ctrlport_req_rd;
|
|
wire unused_fpga_msbs_ctrlport_req_wr;
|
|
wire unused_fpga_msbs_ctrlport_resp_ack;
|
|
wire [31:0] unused_fpga_msbs_ctrlport_resp_data;
|
|
wire [ 1:0] unused_fpga_msbs_ctrlport_resp_status;
|
|
|
|
ctrlport_splitter #(
|
|
.NUM_SLAVES (4)
|
|
) ctrlport_splitter_i (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.s_ctrlport_req_wr (m_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (m_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (m_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (m_ctrlport_req_data),
|
|
.s_ctrlport_req_byte_en (),
|
|
.s_ctrlport_req_has_time (),
|
|
.s_ctrlport_req_time (),
|
|
.s_ctrlport_resp_ack (m_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (m_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (m_ctrlport_resp_data),
|
|
.m_ctrlport_req_wr ({unused_fpga_msbs_ctrlport_req_wr, unused_fpga_intermediate_ctrlport_req_wr, base_reg_ctrlport_req_wr, spi_master_ctrlport_req_wr}),
|
|
.m_ctrlport_req_rd ({unused_fpga_msbs_ctrlport_req_rd, unused_fpga_intermediate_ctrlport_req_rd, base_reg_ctrlport_req_rd, spi_master_ctrlport_req_rd}),
|
|
.m_ctrlport_req_addr ({unused_fpga_msbs_ctrlport_req_addr, unused_fpga_intermediate_ctrlport_req_addr, base_reg_ctrlport_req_addr, spi_master_ctrlport_req_addr}),
|
|
.m_ctrlport_req_data ({unused_fpga_msbs_ctrlport_req_data, unused_fpga_intermediate_ctrlport_req_data, base_reg_ctrlport_req_data, spi_master_ctrlport_req_data}),
|
|
.m_ctrlport_req_byte_en (),
|
|
.m_ctrlport_req_has_time (),
|
|
.m_ctrlport_req_time (),
|
|
.m_ctrlport_resp_ack ({unused_fpga_msbs_ctrlport_resp_ack, unused_fpga_intermediate_ctrlport_resp_ack, base_reg_ctrlport_resp_ack, spi_master_ctrlport_resp_ack}),
|
|
.m_ctrlport_resp_status ({unused_fpga_msbs_ctrlport_resp_status, unused_fpga_intermediate_ctrlport_resp_status, base_reg_ctrlport_resp_status, spi_master_ctrlport_resp_status}),
|
|
.m_ctrlport_resp_data ({unused_fpga_msbs_ctrlport_resp_data, unused_fpga_intermediate_ctrlport_resp_data, base_reg_ctrlport_resp_data, spi_master_ctrlport_resp_data})
|
|
);
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Targets for Requests
|
|
//---------------------------------------------------------------------------
|
|
|
|
wire [15:0] db_clock_divider;
|
|
wire [15:0] mb_clock_divider;
|
|
|
|
cpld_interface_regs #(
|
|
.BASE_ADDRESS (BASE),
|
|
.NUM_ADDRESSES (BASE_SIZE)
|
|
) cpld_interface_regs_i (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.s_ctrlport_req_wr (base_reg_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (base_reg_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (base_reg_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (base_reg_ctrlport_req_data),
|
|
.s_ctrlport_resp_ack (base_reg_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (base_reg_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (base_reg_ctrlport_resp_data),
|
|
.mb_clock_divider (mb_clock_divider),
|
|
.db_clock_divider (db_clock_divider),
|
|
.ipass_enable (ipass_enable),
|
|
.version_info (version_info)
|
|
);
|
|
|
|
ctrlport_spi_master #(
|
|
.CPLD_ADDRESS_WIDTH (15),
|
|
.MB_CPLD_BASE_ADDRESS (MB_CPLD),
|
|
.DB_0_CPLD_BASE_ADDRESS (DB0_CPLD),
|
|
.DB_1_CPLD_BASE_ADDRESS (DB1_CPLD)
|
|
) ctrlport_spi_master_i (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.s_ctrlport_req_wr (spi_master_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (spi_master_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (spi_master_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (spi_master_ctrlport_req_data),
|
|
.s_ctrlport_resp_ack (spi_master_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (spi_master_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (spi_master_ctrlport_resp_data),
|
|
.ss (ss),
|
|
.sclk (sclk),
|
|
.mosi (mosi),
|
|
.miso (miso),
|
|
.mb_clock_divider (mb_clock_divider),
|
|
.db_clock_divider (db_clock_divider)
|
|
);
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Invalid target address spaces
|
|
//---------------------------------------------------------------------------
|
|
|
|
ctrlport_terminator #(
|
|
.START_ADDRESS (BASE + BASE_SIZE),
|
|
.LAST_ADDRESS (MB_CPLD-1)
|
|
) ctrlport_terminator_intermediate (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.s_ctrlport_req_wr (unused_fpga_intermediate_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (unused_fpga_intermediate_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (unused_fpga_intermediate_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (unused_fpga_intermediate_ctrlport_req_data),
|
|
.s_ctrlport_resp_ack (unused_fpga_intermediate_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (unused_fpga_intermediate_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (unused_fpga_intermediate_ctrlport_resp_data)
|
|
);
|
|
|
|
ctrlport_terminator #(
|
|
.START_ADDRESS (DB1_CPLD + DB1_CPLD_SIZE),
|
|
.LAST_ADDRESS (2**CTRLPORT_ADDR_W-1)
|
|
) ctrlport_terminator_msbs (
|
|
.ctrlport_clk (ctrlport_clk),
|
|
.ctrlport_rst (ctrlport_rst),
|
|
.s_ctrlport_req_wr (unused_fpga_msbs_ctrlport_req_wr),
|
|
.s_ctrlport_req_rd (unused_fpga_msbs_ctrlport_req_rd),
|
|
.s_ctrlport_req_addr (unused_fpga_msbs_ctrlport_req_addr),
|
|
.s_ctrlport_req_data (unused_fpga_msbs_ctrlport_req_data),
|
|
.s_ctrlport_resp_ack (unused_fpga_msbs_ctrlport_resp_ack),
|
|
.s_ctrlport_resp_status (unused_fpga_msbs_ctrlport_resp_status),
|
|
.s_ctrlport_resp_data (unused_fpga_msbs_ctrlport_resp_data)
|
|
);
|
|
|
|
endmodule
|
|
|
|
|
|
`default_nettype wire
|
|
|
|
|
|
//XmlParse xml_on
|
|
//<regmap name="PL_CPLD_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
|
|
// <info>
|
|
// This register map is available from the PS via AXI and MPM endpoint.
|
|
// Its size is 128K (17 bits). Only the 17 LSBs are used as address in this documentation.
|
|
// </info>
|
|
// <group name="PL_CPLD_WINDOWS">
|
|
// <window name="BASE" offset="0x0" size="0x40" targetregmap="CPLD_INTERFACE_REGMAP"/>
|
|
// <window name="MB_CPLD" offset="0x8000" size="0x8000" targetregmap="MB_CPLD_PL_REGMAP">
|
|
// <info>
|
|
// All registers of the MB CPLD (PL part).
|
|
// </info>
|
|
// </window>
|
|
// <window name="DB0_CPLD" offset="0x10000" size="0x8000">
|
|
// <info>
|
|
// All registers of the first DB CPLD. Register map will be added later on.
|
|
// </info>
|
|
// </window>
|
|
// <window name="DB1_CPLD" offset="0x18000" size="0x8000">
|
|
// <info>
|
|
// All registers of the second DB CPLD. Register map will be added later on.
|
|
// </info>
|
|
// </window>
|
|
// </group>
|
|
//</regmap>
|
|
//XmlParse xml_off
|