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b210-k7-fpga/sim/rfnoc
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Martin Braun 8af1711952 fpga: rfnoc: Enable blocks with no inputs/outputs 
The following modifications are applied to allow RFNoC blocks with zero
input- or output ports (or none at all):

- The backend interface will no longer synthesize any flushing logic if
  there are no streaming ports
- The Mako templates are modified to allow generating code for blocks
  without streaming ports
- The BFM for RFNoC blocks (RfnocBlockCtrlBfm) is partially factored out
  into a parent class (RfnocBlockCtrlBfmCtrlOnly) which allows the
  simulation of such RFNoC blocks


Original-commit: 878cfcf48f125826e9d48b7c61a4ee7fd19e9a94
2024-05-27 17:05:06 +02:00
..
test/ChdrIfaceBfm
fpga: sim: Workaround Vivado bug in ChdrIfaceBfm_tb
2022-08-25 13:55:30 -05:00
Makefile.srcs
fpga: Remove noc_shell_regs.vh and sim_rfnoc_lib.svh
2022-01-25 14:09:15 -07:00
PkgAxiLiteBfm.sv
fpga: sim: Fix AxiLiteBfm
2020-07-31 13:10:00 -05:00
PkgAxisCtrlBfm.sv
fpga: lib: Add synthesizable AXI4-Stream SV components
2020-06-25 14:44:04 -05:00
PkgAxiStreamBfm.sv
fpga: sim: Support unused tkeep in AxiStreamPacket::dump_bytes()
2022-08-29 17:01:45 -05:00
PkgChdrBfm.sv
fpga: sim: Fix stream command and status models
2020-08-31 08:16:43 -05:00
PkgChdrData.sv
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
PkgChdrIfaceBfm.sv
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
PkgChdrUtils.sv
sim: Parameterize chdr_word_t data type
2020-03-09 13:43:05 -05:00
PkgCtrlIfaceBfm.sv
fpga: sim: Update struct enum initialization
2022-08-25 13:55:30 -05:00
PkgEthernet.sv
fpga: sim: Check for empty packet in clear_unused_bytes
2021-06-17 08:16:59 -05:00
PkgRfnocBlockCtrlBfm.sv
fpga: rfnoc: Enable blocks with no inputs/outputs
2024-05-27 17:05:06 +02:00
PkgRfnocItemUtils.sv
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
PkgTestExec.sv
fpga: sim: Fix test_status indices in PkgTestExec
2024-05-16 09:29:37 -05:00
sim_clock_gen.sv
fpga: sim: Fix typo in clk_wait_f
2022-12-19 08:57:18 -06:00
test_exec.svh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00