274 lines
7.3 KiB
Verilog
274 lines
7.3 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "generic_fifo_ctrl.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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module generic_fifo_ctrl(
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wclk,
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wrst_n,
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wen,
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wfull,
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walmost_full,
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mem_wen,
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mem_waddr,
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rclk,
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rrst_n,
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ren,
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rempty,
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ralmost_empty,
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mem_ren,
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mem_raddr
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);
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//---
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// Parameters
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parameter AWIDTH = 3;
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parameter RAM_DEPTH = (1 << AWIDTH);
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parameter EARLY_READ = 0;
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parameter CLOCK_CROSSING = 1;
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parameter ALMOST_EMPTY_THRESH = 1;
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parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
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//---
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// Ports
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input wclk;
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input wrst_n;
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input wen;
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output wfull;
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output walmost_full;
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output mem_wen;
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output [AWIDTH:0] mem_waddr;
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input rclk;
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input rrst_n;
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input ren;
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output rempty;
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output ralmost_empty;
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output mem_ren;
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output [AWIDTH:0] mem_raddr;
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//---
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// Local declarations
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// Registers
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reg [AWIDTH:0] wr_ptr;
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reg [AWIDTH:0] rd_ptr;
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reg [AWIDTH:0] next_rd_ptr;
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// Combinatorial
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wire [AWIDTH:0] wr_gray;
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reg [AWIDTH:0] wr_gray_reg;
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reg [AWIDTH:0] wr_gray_meta;
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reg [AWIDTH:0] wr_gray_sync;
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reg [AWIDTH:0] wck_rd_ptr;
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wire [AWIDTH:0] wck_level;
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wire [AWIDTH:0] rd_gray;
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reg [AWIDTH:0] rd_gray_reg;
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reg [AWIDTH:0] rd_gray_meta;
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reg [AWIDTH:0] rd_gray_sync;
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reg [AWIDTH:0] rck_wr_ptr;
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wire [AWIDTH:0] rck_level;
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wire [AWIDTH:0] depth;
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wire [AWIDTH:0] empty_thresh;
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wire [AWIDTH:0] full_thresh;
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// Variables
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integer i;
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//---
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// Assignments
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assign depth = RAM_DEPTH[AWIDTH:0];
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assign empty_thresh = ALMOST_EMPTY_THRESH[AWIDTH:0];
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assign full_thresh = ALMOST_FULL_THRESH[AWIDTH:0];
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assign wfull = (wck_level == depth);
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assign walmost_full = (wck_level >= (depth - full_thresh));
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assign rempty = (rck_level == 0);
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assign ralmost_empty = (rck_level <= empty_thresh);
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//---
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// Write Pointer
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always @(posedge wclk or negedge wrst_n)
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begin
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if (!wrst_n) begin
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wr_ptr <= {(AWIDTH+1){1'b0}};
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end
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else if (wen && !wfull) begin
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wr_ptr <= wr_ptr + {{(AWIDTH){1'b0}}, 1'b1};
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end
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end
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//---
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// Read Pointer
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always @(ren, rd_ptr, rck_wr_ptr)
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begin
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next_rd_ptr = rd_ptr;
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if (ren && rd_ptr != rck_wr_ptr) begin
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next_rd_ptr = rd_ptr + {{(AWIDTH){1'b0}}, 1'b1};
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end
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end
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always @(posedge rclk or negedge rrst_n)
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begin
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if (!rrst_n) begin
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rd_ptr <= {(AWIDTH+1){1'b0}};
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end
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else begin
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rd_ptr <= next_rd_ptr;
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end
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end
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//---
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// Binary to Gray conversion
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assign wr_gray = wr_ptr ^ (wr_ptr >> 1);
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assign rd_gray = rd_ptr ^ (rd_ptr >> 1);
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//---
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// Gray to Binary conversion
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always @(wr_gray_sync)
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begin
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rck_wr_ptr[AWIDTH] = wr_gray_sync[AWIDTH];
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for (i = 0; i < AWIDTH; i = i + 1) begin
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rck_wr_ptr[AWIDTH-i-1] = rck_wr_ptr[AWIDTH-i] ^ wr_gray_sync[AWIDTH-i-1];
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end
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end
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always @(rd_gray_sync)
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begin
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wck_rd_ptr[AWIDTH] = rd_gray_sync[AWIDTH];
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for (i = 0; i < AWIDTH; i = i + 1) begin
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wck_rd_ptr[AWIDTH-i-1] = wck_rd_ptr[AWIDTH-i] ^ rd_gray_sync[AWIDTH-i-1];
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end
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end
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//---
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// Clock-Domain Crossing
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generate
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if (CLOCK_CROSSING) begin
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// Instantiate metastability flops
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always @(posedge rclk or negedge rrst_n)
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begin
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if (!rrst_n) begin
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rd_gray_reg <= {(AWIDTH+1){1'b0}};
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wr_gray_meta <= {(AWIDTH+1){1'b0}};
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wr_gray_sync <= {(AWIDTH+1){1'b0}};
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end
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else begin
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rd_gray_reg <= rd_gray;
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wr_gray_meta <= wr_gray_reg;
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wr_gray_sync <= wr_gray_meta;
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end
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end
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always @(posedge wclk or negedge wrst_n)
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begin
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if (!wrst_n) begin
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wr_gray_reg <= {(AWIDTH+1){1'b0}};
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rd_gray_meta <= {(AWIDTH+1){1'b0}};
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rd_gray_sync <= {(AWIDTH+1){1'b0}};
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end
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else begin
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wr_gray_reg <= wr_gray;
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rd_gray_meta <= rd_gray_reg;
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rd_gray_sync <= rd_gray_meta;
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end
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end
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end
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else begin
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// No clock domain crossing
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always @(wr_gray or rd_gray)
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begin
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wr_gray_sync = wr_gray;
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rd_gray_sync = rd_gray;
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end
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end
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endgenerate
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//---
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// FIFO Level
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assign wck_level = wr_ptr - wck_rd_ptr;
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assign rck_level = rck_wr_ptr - rd_ptr;
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//---
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// Memory controls
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assign mem_waddr = wr_ptr;
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assign mem_wen = wen && !wfull;
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generate
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if (EARLY_READ) begin
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// With early read, data will be present at output
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// before ren is asserted. Usufull if we want to add
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// an output register and not add latency.
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assign mem_raddr = next_rd_ptr;
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assign mem_ren = 1'b1;
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end
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else begin
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assign mem_raddr = rd_ptr;
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assign mem_ren = ren;
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end
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endgenerate
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endmodule
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