miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
6 Commits 1 Branch 0 Tags
864a1718c50bae00a360d7ca8665eb86590a9453
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Nicholas Corgan 864a1718c5 Merge branch 'maint' 
Original-commit: 0386a47c431c87aebbf37678315b785284dbe3b9
2014-03-17 07:05:11 -07:00
lib
Pushing the bulk of UHD-3.7.0 code.
2014-02-14 12:05:07 -08:00
sim
Pushing the bulk of UHD-3.7.0 code.
2014-02-14 12:05:07 -08:00
top
Merge branch 'maint'
2014-03-17 07:05:11 -07:00
README.txt
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
2013-10-10 10:17:27 -07:00
vita_chdr.txt
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
2013-10-10 10:17:27 -07:00

README.txt

The file is empty.
Reference in New Issue View Git Blame Copy Permalink
S
Description
No description provided
Readme
84 MiB
Languages
Verilog 42.5%
VHDL 13%
SystemVerilog 12%
HTML 11.1%
C 9.6%
Other 11.6%