205 lines
6.0 KiB
Verilog
205 lines
6.0 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "generic_fifo.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module generic_fifo(
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wclk,
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wrst_n,
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wen,
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wdata,
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wfull,
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walmost_full,
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rclk,
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rrst_n,
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ren,
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rdata,
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rempty,
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ralmost_empty
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);
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//---
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// Parameters
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parameter DWIDTH = 32;
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parameter AWIDTH = 3;
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parameter RAM_DEPTH = (1 << AWIDTH);
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parameter SYNC_WRITE = 1;
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parameter SYNC_READ = 1;
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parameter REGISTER_READ = 0;
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parameter EARLY_READ = 0;
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parameter CLOCK_CROSSING = 1;
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parameter ALMOST_EMPTY_THRESH = 1;
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parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
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parameter MEM_TYPE = `MEM_AUTO_SMALL;
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//---
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// Ports
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input wclk;
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input wrst_n;
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input wen;
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input [DWIDTH-1:0] wdata;
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output wfull;
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output walmost_full;
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input rclk;
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input rrst_n;
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input ren;
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output [DWIDTH-1:0] rdata;
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output rempty;
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output ralmost_empty;
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// Wires
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wire mem_wen;
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wire [AWIDTH:0] mem_waddr;
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wire mem_ren;
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wire [AWIDTH:0] mem_raddr;
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generic_fifo_ctrl #(.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.EARLY_READ (EARLY_READ),
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.CLOCK_CROSSING (CLOCK_CROSSING),
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.ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH),
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.ALMOST_FULL_THRESH (ALMOST_FULL_THRESH)
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)
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ctrl0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (wen),
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.wfull (wfull),
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.walmost_full (walmost_full),
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.mem_wen (mem_wen),
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.mem_waddr (mem_waddr),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (ren),
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.rempty (rempty),
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.ralmost_empty (ralmost_empty),
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.mem_ren (mem_ren),
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.mem_raddr (mem_raddr)
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);
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generate
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if (MEM_TYPE == `MEM_AUTO_SMALL) begin
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generic_mem_small #(.DWIDTH (DWIDTH),
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.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.SYNC_WRITE (SYNC_WRITE),
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.SYNC_READ (SYNC_READ),
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.REGISTER_READ (REGISTER_READ)
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)
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mem0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (mem_wen),
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.waddr (mem_waddr),
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.wdata (wdata),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (mem_ren),
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.roen (ren),
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.raddr (mem_raddr),
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.rdata (rdata)
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);
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end
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if (MEM_TYPE == `MEM_AUTO_MEDIUM) begin
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generic_mem_medium #(.DWIDTH (DWIDTH),
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.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.SYNC_WRITE (SYNC_WRITE),
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.SYNC_READ (SYNC_READ),
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.REGISTER_READ (REGISTER_READ)
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)
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mem0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (mem_wen),
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.waddr (mem_waddr),
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.wdata (wdata),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (mem_ren),
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.roen (ren),
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.raddr (mem_raddr),
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.rdata (rdata)
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);
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end // if (MEM_TYPE == `MEM_AUTO_MEDIUM)
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if (MEM_TYPE == `MEM_AUTO_XILINX) begin
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generic_mem_xilinx_block #(.DWIDTH (DWIDTH),
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.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.SYNC_WRITE (SYNC_WRITE),
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.SYNC_READ (SYNC_READ),
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.REGISTER_READ (REGISTER_READ)
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)
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mem0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (mem_wen),
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.waddr (mem_waddr),
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.wdata (wdata),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (mem_ren),
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.roen (ren),
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.raddr (mem_raddr),
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.rdata (rdata)
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);
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end
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endgenerate
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endmodule
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