141 lines
3.8 KiB
Verilog
141 lines
3.8 KiB
Verilog
`timescale 1ns/1ps
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module new_tx_control_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("new_tx_control_tb.vcd");
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initial $dumpvars(0,new_tx_control_tb);
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initial
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begin
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#1000 reset = 0;
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#30000;
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$finish;
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end
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reg [143:0] tdata;
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reg tlast;
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wire tlast_int;
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reg tvalid = 1'b0;
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wire tready;
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reg [7:0] set_addr;
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reg [31:0] set_data;
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reg set_stb = 1'b0;
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reg [31:0] samp0, samp1;
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task send_packet;
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input [31:0] count;
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input [31:0] start_data;
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input [63:0] send_time;
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input [11:0] pkt_seqnum;
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input eop;
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input eob;
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input send_at;
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input odd;
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begin
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// Send a packet
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samp0 <= start_data;
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samp1 <= start_data + 1;
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@(posedge clk);
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repeat (count-1)
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begin
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tdata <= { 1'b0,send_at,1'b0,1'b0,1'b0,pkt_seqnum,send_time,samp0,samp1 };
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tvalid <= 1;
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samp0 <= samp0 + 2;
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samp1 <= samp1 + 2;
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@(posedge clk);
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end
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tdata <= { odd,send_at,1'b0,eob,eop,pkt_seqnum,send_time,samp0,samp1 };
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@(posedge clk);
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tvalid <= 0;
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@(posedge clk);
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end
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endtask // send_packet
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initial
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begin
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tvalid <= 1'b0;
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while(reset)
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@(posedge clk);
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set_addr <= 8'd0;
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set_data <= 32'd2;
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set_stb <= 1'b1;
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@(posedge clk);
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set_stb <= 1'b0;
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// Single Packet burst, timed
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send_packet(3/*count*/,32'hA000_0000/*data*/,64'h100/*time*/,1/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,0/*odd*/);
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// 2 packet burst, timed
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//send_packet(3/*count*/,32'hB000_0000/*data*/,64'h200/*time*/,2/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,0/*odd*/);
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//send_packet(3/*count*/,32'hC000_0000/*data*/,64'h0/*time*/,3/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,0/*odd*/);
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// single odd packet
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//send_packet(3/*count*/,32'h0A00_0000/*data*/,64'h300/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
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// 2 packet burst, timed, odd
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//send_packet(3/*count*/,32'hD000_0000/*data*/,64'h400/*time*/,5/*SEQ*/,1/*EOP*/,0/*eob*/,1/*timed*/,1/*odd*/);
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//send_packet(3/*count*/,32'hE000_0000/*data*/,64'd0/*time*/,6/*SEQ*/,1/*EOP*/,1/*eob*/,0/*timed*/,1/*odd*/);
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// 2 packet burst, untimed, no eob set
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//send_packet(3/*count*/,32'hF000_0000/*data*/,64'd0/*time*/,7/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
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//send_packet(3/*count*/,32'h9000_0000/*data*/,64'd0/*time*/,8/*SEQ*/,1/*EOP*/,0/*eob*/,0/*timed*/,0/*odd*/);
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// single packet late
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send_packet(3/*count*/,32'hD000_0000/*data*/,64'h0/*time*/,4/*SEQ*/,1/*EOP*/,1/*eob*/,1/*timed*/,1/*odd*/);
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end
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reg [63:0] vita_time;
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wire [31:0] sample;
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wire [143:0] sample_tdata;
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wire sample_tready, sample_tvalid;
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wire [11:0] seqnum;
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wire [31:0] error_code;
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always @(posedge clk)
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if(reset)
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vita_time <= 0;
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else
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vita_time <= vita_time + 1;
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axi_fifo #(.WIDTH(144)) axi_fifo_short
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata(tdata), .i_tvalid(tvalid), .i_tready(tready),
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.o_tdata(sample_tdata), .o_tvalid(sample_tvalid), .o_tready(sample_tready));
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new_tx_control new_tx_control
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(.clk(clk), .reset(reset), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.error(error), .ack(ack), .packet_consumed(consumed), .seqnum(seqnum), .error_code(error_code),
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.sample_tdata(sample_tdata), .sample_tvalid(sample_tvalid), .sample_tready(sample_tready),
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.sample(sample), .run(run), .strobe(strobe),
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.debug()
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);
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assign strobe = run;
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always @(posedge clk)
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begin
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if(strobe)
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$display("%x\t%x", vita_time, sample);
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if(consumed) $display("CONSUMED %x", seqnum);
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if(ack) $display("ACK %x", seqnum);
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if(error) $display("ERROR %x\t%x", seqnum,error_code);
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end
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endmodule // new_tx_control_tb
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