103 lines
2.9 KiB
Verilog
103 lines
2.9 KiB
Verilog
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// Takes 8-bit wide data on a Local-link fifo interface and converts to 64-bit wide axi
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// Parameter START_BYTE controls which byte of the 8 the first incoming byte goes into
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// Use START_BYTE=6 with ethernet to nicely align the words for processing of IP packets
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// Parameter LABEL specifies a value to put in the high word of the very first packet.
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// This is useful for labeling packets with the port it came from so downstream knows
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// how to process it. LABEL gets overwritten if START_BYTE = 0
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module ll8_to_axi64
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#(parameter START_BYTE=6,
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parameter LABEL=8'h00)
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(input clk, input reset, input clear,
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input [7:0] ll_data, input ll_eof, input ll_error, input ll_src_rdy, output ll_dst_rdy,
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output [63:0] axi64_tdata, output axi64_tlast, output [3:0] axi64_tuser, output axi64_tvalid, input axi64_tready);
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wire error_int, eof_int;
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wire [7:0] data_int;
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wire valid_int, ready_int;
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axi_fifo_short #(.WIDTH(10)) ll8_fifo
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(.clk(clk), .reset(reset), .clear(0),
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.i_tdata({ll_error, ll_eof, ll_data}), .i_tvalid(ll_src_rdy), .i_tready(ll_dst_rdy),
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.o_tdata({error_int, eof_int, data_int}), .o_tvalid(valid_int), .o_tready(ready_int),
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.space(), .occupied());
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wire [7:0] label_wire = LABEL; // Enforces parameter width
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reg [3:0] state = START_BYTE;
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reg [63:0] holding; // = {label_wire, 56'h0};
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reg err, eof, done;
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reg [3:0] occ;
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localparam WAIT = 4'd8;
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always @(posedge clk)
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if(reset | clear)
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begin
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state <= START_BYTE;
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holding <= {label_wire, 56'h0};
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err <= 1'b0;
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eof <= 1'b0;
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occ <= 3'd0;
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done <= 1'b0;
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end
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else
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if(state == WAIT)
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begin
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state <= START_BYTE;
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done <= 1'b0;
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holding <= {label_wire, 56'h0};
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end
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else if(valid_int & ready_int)
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begin
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case(state)
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4'd0:
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begin
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holding[63:56] <= data_int;
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holding[55:0] <= 56'h0;
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end
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4'd1: holding[55:48] <= data_int;
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4'd2: holding[47:40] <= data_int;
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4'd3: holding[39:32] <= data_int;
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4'd4: holding[31:24] <= data_int;
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4'd5: holding[23:16] <= data_int;
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4'd6: holding[15:8] <= data_int;
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4'd7: holding[7:0] <= data_int;
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endcase // case (state)
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err <= error_int;
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eof <= eof_int;
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if(error_int | eof_int)
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begin
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occ <= state+1;
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done <= 1'b1;
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state <= WAIT;
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end
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else if (state == 4'd7)
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begin
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occ <= 3'd0;
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done <= 1'b1;
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state <= 4'd0;
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end
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else
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begin
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occ <= 3'd0;
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done <= 1'b0;
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state <= state + 4'd1;
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end // else: !if(state == 4'd7)
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end // if (valid_int & ready_int)
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else
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done <= 1'b0;
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assign axi64_tdata = holding;
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assign axi64_tlast = eof;
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assign axi64_tuser[3] = err;
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assign axi64_tuser[2:0] = occ;
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assign ready_int = axi64_tready & (state != WAIT);
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assign axi64_tvalid = done;
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endmodule // ll8_to_axi64
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