239 lines
6.7 KiB
Verilog
239 lines
6.7 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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//
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// This module is a SIMULATION ONLY bus monitor that probes AXI4-STREAM bus
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// that transfer ETTUS non-CHDR VITA49.0 data, providing logging and diagnostoic info.
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//
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module axi_probe_tb
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#(
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parameter FILENAME="probe.txt",
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parameter VITA_PORT0=0, // UDP ports to identify VITA
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parameter VITA_PORT1=0, // UDP ports to identify VITA
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parameter START_AT_VRL=0 // Flags already stripped back to VRL.
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)
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(
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input clk,
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input reset,
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input clear,
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input [63:0] tdata,
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input tvalid,
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input tready,
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input tlast
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);
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localparam ARP = 16'h0806;
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localparam IPv4 = 16'h0800;
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localparam UDP = 8'h11;
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localparam VRL = 1;
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localparam WAIT_SOF = 0;
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localparam LINE1 = 1;
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localparam LINE2 = 2;
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localparam LINE3 = 3;
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localparam LINE4 = 4;
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localparam LINE5 = 5;
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localparam LINE6 = 6;
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localparam LINE7 = 7;
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localparam WAIT_EOF = 15;
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reg [3:0] out_state;
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reg [63:0] last_line;
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reg [15:0] eth_proto;
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reg [7:0] ip_proto;
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reg vita_proto;
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integer dump_file;
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initial
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begin
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dump_file = $fopen(FILENAME,"w");
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end
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//
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// Monitor packets leaving FIFO
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//
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always @(posedge clk)
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if (reset | clear) begin
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out_state <= WAIT_SOF;
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end else
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case(out_state)
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//
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// After RESET or the EOF of previous packet, the first cycle with
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// output valid asserted is the SOF and presents the Header word.
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// The cycle following the concurrent presentation of asserted output
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// valid and output ready presents the word following the header.
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//
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WAIT_SOF:
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if (tvalid && tready) begin
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last_line <= 0;
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eth_proto <= 0;
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ip_proto <= 0;
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vita_proto <= 0;
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$fdisplay(dump_file,"------------------------------------------");
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$fdisplay(dump_file,"Time = %1d",$time);
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if (START_AT_VRL) begin
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if (tdata[63:32] == "VRLP") begin
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$fdisplay(dump_file,"VRL VITA49 PAYLOAD");
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vita_proto <= VRL;
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end
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out_state <= LINE7;
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end
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else out_state <= LINE1;
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last_line <= tdata;
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end else begin
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out_state <= WAIT_SOF;
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end
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//
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LINE1: if (tvalid && tready) begin
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$fdisplay(dump_file,"Dst MAC: %x:%x:%x:%x:%x:%x",
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last_line[15:8],last_line[7:0],tdata[63:56],tdata[55:48],tdata[47:40],tdata[39:32]);
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last_line = tdata;
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out_state <= LINE2;
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end
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//
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LINE2: if (tvalid && tready) begin
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$fdisplay(dump_file,"Src MAC: %x:%x:%x:%x:%x:%x",
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last_line[31:24],last_line[23:16],last_line[15:8],last_line[7:0],
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tdata[63:56],tdata[55:48]);
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eth_proto = tdata[47:32];
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// Protocol??
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if (tdata[47:32] == ARP) begin
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//ARP
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$fdisplay(dump_file,"ARP packet");
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if (tdata[31:16] == 'h0001)
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$fdisplay(dump_file,"HTYPE = 1 (Ethernet)");
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if (tdata[31:16] == 'h0800)
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$fdisplay(dump_file,"PTYPE = 0x0800 (IPv4)");
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out_state <= LINE3;
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end else if (tdata[47:32] == IPv4) begin
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// IPv4
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$fdisplay(dump_file,"IPv4 packet");
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$fdisplay(dump_file,"Packet Length: %1d",tdata[15:0]);
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out_state <= LINE3;
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end else
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out_state <= WAIT_EOF;
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end // case: LINE2
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//
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LINE3:
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if (tvalid && tready) begin
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// Protocol??
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if (eth_proto == ARP) begin
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$fdisplay(dump_file,"HLEN: %d PLEN: %d",tdata[63:56],tdata[55:48]);
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if (tdata[47:32] == 1) $fdisplay(dump_file,"Operation: ARP REQUEST");
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else if (tdata[47:32] == 2) $fdisplay(dump_file,"Operation: ARP REPLY");
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else $fdisplay(dump_file,"Operation: UNKNOWN");
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last_line = tdata;
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// out_state <= LINE4;
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out_state <= WAIT_EOF; // Add further ARP decode later if desired.
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end else if (eth_proto == IPv4) begin
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ip_proto = tdata[23:16];
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if (tdata[23:16] == UDP) $fdisplay(dump_file,"IPv4 Protocol: UDP");
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else $fdisplay(dump_file,"IPv4 Protocol: %x",tdata[23:16]);
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out_state <= LINE4;
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end else
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out_state <= WAIT_EOF;
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end // if (tvalid && tready)
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//
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LINE4:
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if (tvalid && tready) begin
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// Protocol??
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if (eth_proto == IPv4) begin
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$fdisplay(dump_file,"IP Src Address: %1d.%1d.%1d.%1d IP Dst Address: %1d.%1d.%1d.%1d",
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tdata[63:56],tdata[55:48],tdata[47:40],tdata[39:32],
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tdata[31:24],tdata[23:16],tdata[15:8],tdata[7:0]);
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if (ip_proto == UDP)
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out_state <= LINE5;
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else
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out_state <= WAIT_EOF;
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end
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end // if (tvalid && tready)
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//
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LINE5:
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if (tvalid && tready) begin
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// Protocol??
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if (ip_proto == UDP) begin
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$fdisplay(dump_file,"UDP Src Port: %d UDP Dst Port: %d",
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tdata[63:48],tdata[47:32]);
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$fdisplay(dump_file,"UDP Length: %1d",tdata[31:16]);
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last_line = tdata;
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out_state <= LINE6;
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end
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end // if (tvalid && tready)
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//
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LINE6:
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if (tvalid && tready) begin
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// Protocol??
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if (tdata[63:32] == "VRLP") begin
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$fdisplay(dump_file,"VRL VITA49 PAYLOAD");
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// Expand VITA decode later
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vita_proto <= VRL;
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out_state <= LINE7;
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end
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end // if (tvalid && tready)
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//
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LINE7:
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if (tvalid && tready) begin
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// Protocol??
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if (vita_proto == VRL) begin
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$fdisplay(dump_file,"VRT: Packet Size: %1d StreamID: %x",tdata[47:32],tdata[31:0]);
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out_state <= WAIT_EOF;
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end
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if (tlast) begin
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$fdisplay(dump_file,"------------------------------------------");
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out_state <= WAIT_SOF;
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end
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end // if (tvalid && tready)
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//
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// EOF is signalled by o_tlast asserted whilst output valid and ready asserted.
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//
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WAIT_EOF:
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if (tlast && tvalid && tready) begin
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out_state <= WAIT_SOF;
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end else begin
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out_state <= WAIT_EOF;
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end
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endcase // case(in_state)
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endmodule // axi_probe_tb
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