90 lines
2.4 KiB
Verilog
90 lines
2.4 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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`timescale 500ps/1ps
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module pcie_dma_ctrl_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial begin
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#100 reset = 0;
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#200000;
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$finish;
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end
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function [63:0] iop2_msg_write;
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input [19:0] address;
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input [31:0] data;
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input half_wd;
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begin
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// {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
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iop2_msg_write = {1'b0, 1'b1, 1'b0, half_wd, 8'h00, address, data};
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end
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endfunction // iop2_msg_write
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function [63:0] iop2_msg_read;
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input [19:0] address;
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input half_wd;
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begin
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// {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
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iop2_msg_read = {1'b0, 1'b0, 1'b1, half_wd, 8'h00, address, 32'h0};
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end
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endfunction // iop2_msg_read
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wire [3:0] clear;
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wire [63:0] frame_size;
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reg [3:0] pkt_stb = 0;
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reg [3:0] samp_stb = 0;
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reg [3:0] error = 0;
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reg [7:0] rtr_sid = 4;
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wire [3:0] rtr_dst;
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reg [63:0] regi_tdata;
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reg regi_tvalid;
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wire regi_tready;
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wire [63:0] rego_tdata;
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wire rego_tvalid;
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reg rego_tready;
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reg [31:0] rego_payload;
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always @(posedge clk)
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if (rego_tdata[63] & rego_tvalid & rego_tready)
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rego_payload <= rego_tdata[31:0];
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initial begin
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regi_tvalid <= 0;
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rego_tready <= 0;
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while (reset) @(posedge clk);
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rego_tready <= 1;
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@(posedge clk);
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regi_tdata <= iop2_msg_write(20'h304, 32'hA, 0);
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regi_tvalid <= 1;
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@(posedge clk);
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while (~regi_tready) @(posedge clk);
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regi_tvalid <= 0;
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@(posedge clk);
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end // initial begin
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pcie_dma_ctrl #(
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.NUM_STREAMS(4), .FRAME_SIZE_W(16),
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.REG_BASE_ADDR(20'h00200), .ENABLE_ROUTER(1),
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.ROUTER_SID_W(8), .ROUTER_DST_W(4)
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) dut (
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.clk(clk), .reset(reset),
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.regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(regi_tready),
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.rego_tdata(rego_tdata), .rego_tvalid(rego_tvalid), .rego_tready(rego_tready),
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.set_clear(clear), .set_frame_size(frame_size), .sample_stb(samp_stb), .packet_stb(pkt_stb),
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.stream_err(error), .rtr_sid(rtr_sid), .rtr_dst(rtr_dst)
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);
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endmodule
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