107 lines
2.7 KiB
Verilog
107 lines
2.7 KiB
Verilog
`timescale 1ns/1ps
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module axi_packet_gate_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("axi_packet_gate_tb.vcd");
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initial $dumpvars(0,axi_packet_gate_tb);
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task send_packet;
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input [63:0] data_start;
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input [2:0] user;
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input [31:0] len;
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input error;
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begin
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// Send a packet
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@(posedge clk);
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{i_terror, i_tuser, i_tlast, i_tdata} <= { 1'b0, user, 1'b0, data_start };
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repeat(len-1)
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begin
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i_tvalid <= 1;
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@(posedge clk);
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i_tdata <= i_tdata + 1;
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end
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i_tlast <= 1;
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i_terror <= error;
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i_tdata <= i_tdata + 1;
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@(posedge clk);
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i_tvalid <= 1'b0;
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@(posedge clk);
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end
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endtask // send_packet
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initial
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begin
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#1000 reset = 0;
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#200000;
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$finish;
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end
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wire [63:0] o_tdata;
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reg [63:0] i_tdata;
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wire [2:0] o_tuser;
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reg [2:0] i_tuser;
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reg i_tlast;
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wire o_tlast;
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wire o_tvalid, i_tready;
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reg i_tvalid, o_tready;
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reg i_terror;
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localparam RPT_COUNT = 16;
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initial
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begin
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i_tvalid <= 0;
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o_tready <= 0;
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while(reset)
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@(posedge clk);
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@(posedge clk);
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send_packet(64'hA0,3'd0, 16, 0);
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send_packet(64'hB0,3'd0, 16, 0);
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o_tready <= 1;
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send_packet(64'hC0,3'd0, 16, 1);
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send_packet(64'hD0,3'd0, 16, 0);
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send_packet(64'hE0,3'd0, 16, 0);
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send_packet(64'hF0,3'd0, 16, 0);
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@(posedge clk);
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end // initial begin
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wire i_terror_int, i_tlast_int, i_tready_int, i_tvalid_int;
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wire [2:0] i_tuser_int;
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wire [63:0] i_tdata_int;
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wire o_tlast_int, o_tready_int, o_tvalid_int;
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wire [2:0] o_tuser_int;
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wire [63:0] o_tdata_int;
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axi_fifo #(.WIDTH(69), .SIZE(10)) fifo
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({i_terror,i_tlast,i_tuser,i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata({i_terror_int,i_tlast_int,i_tuser_int,i_tdata_int}), .o_tvalid(i_tvalid_int), .o_tready(i_tready_int));
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axi_packet_gate #(.WIDTH(67), .SIZE(10)) dut
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({i_tuser_int,i_tdata_int}), .i_terror(i_terror_int), .i_tlast(i_tlast_int), .i_tvalid(i_tvalid_int), .i_tready(i_tready_int),
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.o_tdata({o_tuser_int,o_tdata_int}), .o_tlast(o_tlast_int), .o_tvalid(o_tvalid_int), .o_tready(o_tready_int));
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axi_fifo #(.WIDTH(68), .SIZE(10)) fifo_out
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(.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({o_tlast_int,o_tuser_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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.o_tdata({o_tlast,o_tuser,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready));
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always @(posedge clk)
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if(o_tvalid & o_tready)
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$display("TUSER %x\tTLAST %x\tTDATA %x",o_tuser,o_tlast, o_tdata);
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endmodule // axi_packet_gate_tb
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