170 lines
3.7 KiB
Verilog
170 lines
3.7 KiB
Verilog
//
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// Copyright 2012-2013 Ettus Research LLC
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//
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// Block RAM AXI fifo
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// Special case SIZE <= 5 uses a short fifo
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module axi_fifo
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#(parameter WIDTH=32, SIZE=9)
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(input clk, input reset, input clear,
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input [WIDTH-1:0] i_tdata,
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input i_tvalid,
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output i_tready,
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output [WIDTH-1:0] o_tdata,
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output o_tvalid,
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input o_tready,
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output reg [15:0] space,
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output reg [15:0] occupied);
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generate
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if(SIZE<=5) begin
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wire [5:0] space_short, occupied_short;
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axi_fifo_short #(.WIDTH(WIDTH)) fifo_short
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(
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.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(i_tdata), .i_tvalid(i_tvalid), .i_tready(i_tready),
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.o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(space_short), .occupied(occupied_short)
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);
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always @* space <= {10'b0, space_short};
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always @* occupied <= {10'b0, occupied_short};
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end
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else begin
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wire write = i_tvalid & i_tready;
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wire read = o_tvalid & o_tready;
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wire full, empty;
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assign i_tready = ~full;
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assign o_tvalid = ~empty;
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// Read side states
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localparam EMPTY = 0;
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localparam PRE_READ = 1;
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localparam READING = 2;
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reg [SIZE-1:0] wr_addr, rd_addr;
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reg [1:0] read_state;
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reg empty_reg, full_reg;
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always @(posedge clk)
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if(reset)
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wr_addr <= 0;
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else if(clear)
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wr_addr <= 0;
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else if(write)
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wr_addr <= wr_addr + 1;
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ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
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ram (.clka(clk),
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.ena(1'b1),
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.wea(write),
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.addra(wr_addr),
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.dia(i_tdata),
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.doa(),
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.clkb(clk),
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.enb((read_state==PRE_READ)|read),
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.web(1'b0),
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.addrb(rd_addr),
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.dib({WIDTH{1'b1}}),
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.dob(o_tdata));
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always @(posedge clk)
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if(reset)
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begin
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read_state <= EMPTY;
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rd_addr <= 0;
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empty_reg <= 1;
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end
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else
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if(clear)
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begin
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read_state <= EMPTY;
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rd_addr <= 0;
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empty_reg <= 1;
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end
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else
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case(read_state)
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EMPTY :
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if(write)
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begin
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//rd_addr <= wr_addr;
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read_state <= PRE_READ;
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end
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PRE_READ :
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begin
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read_state <= READING;
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empty_reg <= 0;
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rd_addr <= rd_addr + 1;
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end
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READING :
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if(read)
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if(rd_addr == wr_addr)
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begin
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empty_reg <= 1;
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if(write)
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read_state <= PRE_READ;
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else
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read_state <= EMPTY;
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end
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else
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rd_addr <= rd_addr + 1;
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endcase // case(read_state)
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wire [SIZE-1:0] dont_write_past_me = rd_addr - 2;
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wire becoming_full = wr_addr == dont_write_past_me;
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always @(posedge clk)
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if(reset)
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full_reg <= 0;
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else if(clear)
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full_reg <= 0;
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else if(read & ~write)
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full_reg <= 0;
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//else if(write & ~read & (wr_addr == (rd_addr-3)))
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else if(write & ~read & becoming_full)
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full_reg <= 1;
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//assign empty = (read_state != READING);
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assign empty = empty_reg;
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// assign full = ((rd_addr - 1) == wr_addr);
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assign full = full_reg;
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//////////////////////////////////////////////
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// space and occupied are for diagnostics only
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// not guaranteed exact
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localparam NUMLINES = (1<<SIZE);
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always @(posedge clk)
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if(reset)
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space <= NUMLINES;
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else if(clear)
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space <= NUMLINES;
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else if(read & ~write)
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space <= space + 16'b1;
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else if(write & ~read)
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space <= space - 16'b1;
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always @(posedge clk)
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if(reset)
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occupied <= 16'b0;
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else if(clear)
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occupied <= 16'b0;
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else if(read & ~write)
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occupied <= occupied - 16'b1;
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else if(write & ~read)
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occupied <= occupied + 16'b1;
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end
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endgenerate
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endmodule // fifo_long
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