26 lines
391 B
Verilog
26 lines
391 B
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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module por_gen
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(input clk,
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output reset_out);
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reg por_rst;
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reg [7:0] por_counter = 8'h0;
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always @(posedge clk)
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if (por_counter != 8'h55)
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begin
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por_counter <= por_counter + 8'h1;
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por_rst <= 1'b1;
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end
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else
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por_rst <= 1'b0;
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assign reset_out = por_rst;
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endmodule // por_gen
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