315 lines
7.6 KiB
Verilog
315 lines
7.6 KiB
Verilog
//
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// Synthesizable test pattern generators and checkers
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// for CHDR that can be used to test transparent blocks
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// (FIFOs, switches, etc)
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//
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//`define MTU 8192
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`define MTU 1536
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module axi_chdr_test_pattern
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(
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input clk,
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input reset,
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//
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// CHDR friendly AXI stream input
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//
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output reg [63:0] i_tdata,
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output reg i_tlast,
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output reg i_tvalid,
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input wire i_tready,
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//
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// CHDR friendly AXI Stream output
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//
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input wire [63:0] o_tdata,
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input wire o_tlast,
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input wire o_tvalid,
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output reg o_tready,
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//
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// Test flags
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//
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input start,
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input [15:0] control,
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output reg fail,
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output reg done
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);
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wire [7:0] bist_rx_delay = control[7:0];
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wire [7:0] bist_tx_delay = control[15:8];
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reg [15:0] tx_count, rx_count;
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reg [15:0] tx_data, rx_data;
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reg [7:0] tx_delay, rx_delay;
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localparam TX_IDLE = 0;
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localparam TX_START = 1;
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localparam TX_ACTIVE = 2;
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localparam TX_GAP = 3;
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localparam TX_DONE = 4;
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localparam TX_WAIT = 5;
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localparam RX_IDLE = 0;
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localparam RX_ACTIVE = 1;
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localparam RX_FAIL = 2;
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localparam RX_DONE = 3;
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localparam RX_WAIT = 4;
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reg [2:0] tx_state, rx_state;
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//
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// Transmitter
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//
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always @(posedge clk)
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if (reset)
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begin
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tx_delay <= 0;
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tx_count <= 8;
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tx_data <= 0;
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i_tdata <= 64'h0;
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i_tlast <= 1'b0;
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i_tvalid <= 1'b0;
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tx_state <= TX_IDLE;
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end
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else
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begin
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case(tx_state)
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TX_IDLE: begin
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tx_delay <= 0;
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i_tdata <= 64'h0;
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i_tlast <= 1'b0;
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i_tvalid <= 1'b0;
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tx_data <= 0;
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tx_count <= 4;
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// Run whilst start asserted.
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if (start) begin
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tx_state <= TX_START;
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// ....Go back to initialized state if start deasserted.
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end else begin
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tx_state <= TX_IDLE;
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end
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end // case: TX_IDLE
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//
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// START signal is asserted.
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// Now need to start transmiting a packet.
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//
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TX_START: begin
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// At the next clock edge drive first beat of new packet onto HDR bus.
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i_tlast <= 1'b0;
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i_tvalid <= 1'b1;
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tx_data <= tx_data + 4;
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// i_tdata <= {tx_data,tx_data+16'd1,tx_data+16'd2,tx_data+16'd3};
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i_tdata <= {4{(tx_data[2]?16'hffff:16'h0000)^tx_data[15:0]}};
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tx_state <= TX_ACTIVE;
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end
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//
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// Valid data is (already) being driven onto the CHDR bus.
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// i_tlast may also be driven asserted if current data count has reached EOP.
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// Watch i_tready to see when it's consumed.
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// When packets are consumed increment data counter or transition state if
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// EOP has sucsesfully concluded.
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//
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TX_ACTIVE: begin
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i_tvalid <= 1'b1; // Always assert tvalid
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if (i_tready) begin
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// i_tdata <= {tx_data,tx_data+16'd1,tx_data+16'd2,tx_data+16'd3};
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i_tdata <= {4{(tx_data[2]?16'hffff:16'h0000)^tx_data[15:0]}};
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// Will this next beat be the last in a packet?
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if (tx_data == tx_count) begin
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tx_data <= 0;
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i_tlast <= 1'b1;
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tx_state <= TX_GAP;
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end else begin
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tx_data <= tx_data + 4;
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i_tlast <= 1'b0;
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tx_state <= TX_ACTIVE;
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end
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end else begin
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// Keep driving all CHDR bus signals as-is until i_tready is asserted.
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tx_state <= TX_ACTIVE;
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end
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end // case: TX_ACTIVE
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//
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// Force an inter-packet gap between packets in a BIST sequence where tvalid is driven low.
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// As we leave this state check if all packets in BIST sequence have been generated yet,
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// and if so go to done state.
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//
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TX_GAP: begin
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if (i_tready) begin
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i_tvalid <= 1'b0;
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i_tdata <= 64'h0;
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i_tlast <= 1'b0;
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tx_count <= tx_count + 4;
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if (tx_count < `MTU) begin
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tx_state <= TX_WAIT;
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tx_delay <= bist_tx_delay;
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end else
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tx_state <= TX_DONE;
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end else begin // if (i_tready)
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tx_state <= TX_GAP;
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end
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end // case: TX_GAP
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//
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// Simulate inter packet gap in real UHD system
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TX_WAIT: begin
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if (tx_delay == 0)
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tx_state <= TX_START;
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else begin
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tx_delay <= tx_delay - 1;
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tx_state <= TX_WAIT;
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end
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end
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//
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// Complete test pattern BIST sequence has been transmitted. Sit in this
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// state indefinately if START is taken low, which re-inits the whole BIST solution.
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//
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TX_DONE: begin
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if (!start) begin
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tx_state <= TX_DONE;
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end else begin
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tx_state <= TX_IDLE;
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end
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i_tvalid <= 1'b0;
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i_tdata <= 64'd0;
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i_tlast <= 1'b0;
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end
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endcase // case (tx_state)
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end
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//
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// Receiver
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//
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always @(posedge clk)
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if (reset)
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begin
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rx_delay <= 0;
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rx_count <= 0;
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rx_data <= 0;
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o_tready <= 1'b0;
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rx_state <= RX_IDLE;
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fail <= 1'b0;
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done <= 1'b0;
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end
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else begin
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case (rx_state)
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RX_IDLE: begin
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rx_delay <= 0;
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o_tready <= 1'b0;
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rx_data <= 0;
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rx_count <= 4;
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fail <= 1'b0;
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done <= 1'b0;
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// Not accepting data whilst Idle,
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// switch to active when packet arrives
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if (o_tvalid) begin
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o_tready <= 1'b1;
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rx_state <= RX_ACTIVE;
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end else
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rx_state <= RX_IDLE;
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end
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RX_ACTIVE: begin
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o_tready <= 1'b1;
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if (o_tvalid)
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// if (o_tdata != {rx_data,rx_data+16'd1,rx_data+16'd2,rx_data+16'd3})
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if (o_tdata != {4{(rx_data[2]?16'hffff:16'h0000)^rx_data[15:0]}})
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begin
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$display("o_tdata: %x != expected: %x @ time: %d",o_tdata,
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// {rx_data,rx_data+16'd1,rx_data+16'd2,rx_data+16'd3},
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{4{(rx_data[2]?16'hffff:16'h0000)^rx_data[15:0]}},
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$time);
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rx_state <= RX_FAIL;
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end
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else
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// Should last be asserted?
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if (rx_data == rx_count)
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// ...last not asserted when it should be!
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if (~(o_tlast===1)) begin
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$display("o_tlast not asserted when it should be @ time: %d",$time);
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rx_state <= RX_FAIL;
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end else begin
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// End of packet, set up to RX next
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rx_data <= 0;
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rx_count <= rx_count + 4;
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rx_delay <= bist_rx_delay;
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if (rx_count == `MTU) begin
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rx_state <= RX_DONE;
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end else begin
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rx_state <= RX_WAIT;
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end
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o_tready <= 1'b0;
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end
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else
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// ...last asserted when it should not be!
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if (~(o_tlast===0)) begin
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$display("o_tlast asserted when it should not be @ time: %d",$time);
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rx_state <= RX_FAIL;
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end else begin
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// Still in packet body
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rx_data <= rx_data + 4;
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rx_delay <= bist_rx_delay;
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rx_state <= RX_WAIT;
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o_tready <= 1'b0;
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end
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else
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// Nothing to do this cycle
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rx_state <= RX_ACTIVE;
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end // case: RX_ACTIVE
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// To simulate the radio consuming samples at a steady rate set by the decimation
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// have a programable delay here
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RX_WAIT: begin
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if (rx_delay == 0) begin
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rx_state <= RX_ACTIVE;
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o_tready <= 1'b1;
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end else begin
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rx_delay <= rx_delay - 1;
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rx_state <= RX_WAIT;
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end
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end
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RX_FAIL: begin
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o_tready <= 1'b0;
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done <= 1'b1;
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fail <= 1'b1;
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// If start is deasserted allow BIST logic to reset and rearm
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if (start)
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rx_state <= RX_FAIL;
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else
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rx_state <= RX_IDLE;
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end
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RX_DONE: begin
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o_tready <= 1'b0;
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done <= 1'b1;
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fail <= 1'b0;
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// If start is asserted allow BIST logic to reset, rearm & restart
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if (!start)
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rx_state <= RX_DONE;
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else
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rx_state <= RX_IDLE;
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end
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endcase // case (rx_state)
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end
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endmodule
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