57 lines
1.6 KiB
Plaintext
57 lines
1.6 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.3
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# Date: Fri Dec 21 21:52:41 2012
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.4
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc7k410t
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SET devicefamily = kintex7
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ffg900
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SET removerpms = false
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SET simulationfiles = Structural
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.4
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# END Select
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# BEGIN Parameters
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CSET auto_negotiation=false
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CSET component_name=gige_sfp
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CSET management_interface=false
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CSET physical_interface=Transceiver
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CSET sgmii_mode=10_100_1000
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CSET sgmii_phy_mode=false
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CSET standard=1000BASEX
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CSET timing_sim=false
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CSET transceiver_tile=A
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-06-05T17:19:16Z
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# END Extra information
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GENERATE
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# CRC: 9dc62bf3
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