50 lines
1.4 KiB
Plaintext
50 lines
1.4 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.4
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# Date: Thu Jan 17 18:44:40 2013
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:mig_7series:1.8
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc7k410t
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SET devicefamily = kintex7
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SET flowvendor = Foundation_ISE
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = ffg900
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT MIG_7_Series family Xilinx,_Inc. 1.8
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# END Select
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# BEGIN Parameters
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CSET component_name=ddr3_interface_fast
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CSET xml_input_file=./ddr3_interface_fast/mig.prj
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2012-12-18T05:23:34Z
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# END Extra information
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GENERATE
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# CRC: 84a5b072
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